Solid State Metallurgical Diffusion and Intermetallic Growth during Sustained Component Baking

Boundary

Intermetallic growth during component dry baking transforms terminal metallization from a ductile solderable interface into an oxidized, brittle intermetallic boundary layer. SMT lines handling high-reliability sensors run sustained component dry bakes at 125 degrees Celsius to reset the moisture exposure clock under JEDEC J-STD-033 before board placement. This thermal intervention drives solid-state diffusion across leadframe base metals, underplate barriers, and terminal finishes.

Tin finishes consuming their copper substrates form binary intermetallic compounds directly inside the floor-stock baking oven. The resulting intermetallic layer depletes the free surface tin required to establish capillary action and meniscus wetting during surface-mount reflow.

Solid-state diffusion moves metal atoms across the interface down chemical potential gradients without liquid phases. In lead-free tin-plated copper leadframes, copper atoms diffuse into the electroplated matte tin via interstitial pathways, producing intermetallic compounds at rates governed by temperature and dwell duration. Sustained exposure at 125 degrees Celsius accelerates this atomic migration compared to room temperature storage, converting the active soldering layer into Cu6Sn5 and Cu3Sn.

A plated terminal carrying a nominal 7.00 micrometer finish can experience intermetallic front progression exceeding 1.50 micrometers during an extended bake cycle. Solderability degrades irreversibly when this growth front breaches the external surface.

Plated terminations with excessive intermetallic growth face catastrophic wetting failure during board assembly. Liquid SAC305 solder wets virgin tin within 0.8 seconds at 245 degrees Celsius. In contrast, copper-tin intermetallics exposed to furnace atmospheres oxidize instantly into non-wetting tin oxides and copper oxides.

Molten solder fails to reduce these refractory surface oxides under standard no-clean flux chemistries. The line then records non-wetting, dewetting, solder balling, and side-fillet starvation on bottom-terminated components such as QFN, DFN, and land grid arrays.

Terminal solderability fails during reflow once solid-state intermetallic growth consumes the outer electroplated tin layer and exposes oxidized intermetallics to ambient furnace gas.

Intermetallic consumption operates as a destructive penalty for moisture removal. Moisture desorption runs on Fickian diffusion kinetics through polyimide and epoxy mold compounds, requiring elevated thermal energy to drive water molecules out of plastic packages before reflow. The thermal energy expediting moisture desorption simultaneously drives solid-state intermetallic phase transformation within the copper-tin, nickel-tin, and gold-aluminum metallization systems.

Floor managers balancing moisture risk against termination solderability face a narrow operational window. Setting baking profiles without verified diffusion boundary models sacrifices component termination solderability to satisfy component dry-pack constraints.

Lattice

Atomic movement across solid metal interfaces operates through vacancies and interstitial sites within the crystalline lattice. Fickian diffusion equations dictate the flux of solute atoms moving through the terminal barrier layers. Temperature functions as an exponential driver of the diffusion coefficient within the classic Arrhenius relationship.

Elevating the temperature from 25 degrees Celsius to 125 degrees Celsius elevates solid-state diffusion velocities by several orders of magnitude, collapsing months of room-temperature aging into days of sustained oven dwell.

Phase evolution in copper-tin interfaces proceeds sequentially across the metallurgical boundary. The eta-phase Cu6Sn5 nucleates initially along the interface grain boundaries, exhibiting scallop-like morphology extending into the electroplated tin deposit. Prolonged baking supplies the activation energy required to nucleate the epsilon-phase Cu3Sn compound between the parent copper substrate and the Cu6Sn5 layer.

Cu3Sn nucleates when local tin concentration drops below stoichiometric thresholds and thermal activation overcomes the nucleation barrier of roughly 100 kilojoules per mole. This epsilon phase grows as a planar band, acting as a planar diffusion layer that governs subsequent atom transfer.

Thickness evolution of the composite intermetallic layer follows a parabolic growth law governed by square-root-of-time kinetics. The total thickness X after baking dwell duration t at absolute temperature T complies with the governing relationship:

X = X0 + (D0 exp(-Q / (R T)) t)^0.5

Where X0 represents the initial intermetallic thickness following electroplating, D0 is the intrinsic diffusion frequency factor, Q designates the activation energy for intermetallic growth, R is the universal gas constant, and T is the bake temperature in Kelvin. The apparent activation energy for total intermetallic growth in electroplated matte tin over copper leadframes ranges between 0.85 and 1.05 electron-volts, depending directly on grain size and crystal texture within the electroplated tin layer.

Leadframe substrates lacking an effective diffusion barrier suffer rapid consumption of active tin plating. Nickel-plated barrier layers alter this diffusion profile by introducing a dense face-centered cubic lattice that inhibits copper atom migration. The nickel-tin intermetallic Ni3Sn4 develops at roughly one-tenth the volumetric rate of copper-tin intermetallics under identical 125 degrees Celsius conditions.

Bypassing a nickel barrier layer directly exposes the thin tin termination to uncontrolled copper migration, driving accelerated consumption during component re-baking procedures.

Grain boundary diffusion dominates over lattice diffusion at baking temperatures below the absolute melting point homologous ratio of 0.6. Electroplated matte tin features high grain boundary density across column structures. Tin atoms provide fast diffusion conduits along these defective boundaries, accelerating copper solute penetration toward the exterior surface.

Controlling the grain structure during leadframe barrel plating limits the path density for this low-temperature atomic transport.

Bake

Floor exposure limits outlined in JEDEC J-STD-033 dictate component baking intervals based on moisture sensitivity levels, package thickness, and ambient shop floor relative humidity. Standard factory practice treats 125 degrees Celsius as the standard thermal setting for rapid moisture reset without melting standard shipping trays. High-temperature carrier trays rated for 150 degrees Celsius permit continuous baking, while lower-grade trays demand component de-reeling or re-traying into metal cassettes.

Baking intervals span from 48 hours for thin packages up to 96 hours for thick plastic power packages and complex sensor modules.

Sustained thermal exposure accelerates intermetallic formation throughout the drying window. A matte tin finish with an initial thickness of 5.00 micrometers plus or minus 1.00 micrometer exhibits approximately 0.50 micrometers of as-plated Cu6Sn5 intermetallic compound. Maintaining this component inside a baking oven at 125 degrees Celsius for 96 hours increases the total intermetallic thickness to 2.20 micrometers.

This progression leaves less than 3.00 micrometers of unreacted surface tin, lowering the thermal protection margin during subsequent factory reflow passes.

A 96-hour component bake at 125 degrees Celsius expands the copper-tin intermetallic zone past 2.00 micrometers, halving the unreacted tin finish thickness.

Multiple baking cycles generate cumulative metallurgical degradation across lead terminations. Operators baking components through three consecutive floor-life expiration resets accumulate 288 hours of exposure at 125 degrees Celsius. Under these conditions, intermetallic consumption reaches 3.80 micrometers.

The remaining free tin layer drops below 1.20 micrometers, exposing leadframes to surface oxidation and wetting termination collapse. Production lines running cumulative bakes without tracking total thermal dwell systematically induce termination wetting failure on parts that still pass incoming visual inspection.

Plating chemistry and deposition topography govern the practical diffusion rate during oven dwells. Electroplated matte tin deposits containing organic brighteners display refined, small grain boundaries that multiply diffusion conduits. Bright tin finishes undergo intermetallic growth rates up to 40 percent faster than carbon-free matte tin finishes during identical baking schedules.

Matte tin formulations holding grain diameters between 1.00 and 5.00 micrometers provide superior stability against intermetallic expansion during floor-life resets.

Package handling during the bake phase imposes mechanical risks alongside metallurgical diffusion. Leadframes subjected to high-temperature baking undergo thermal expansion mismatches between the copper leadframe base, epoxy mold compound, and external transport fixtures. Differential expansion introduces shear strain across the lead interface.

This mechanical shear promotes micro-cracking across brittle intermetallic boundaries, generating void networks along the leadframe heel and shoulder surfaces.

Voiding

Kirkendall void formation represents a severe structural failure mode tied directly to unbalanced solid-state diffusion. Diffusion rates of individual metal species through intermetallic layers are rarely equivalent. Copper atoms diffuse outward through the Cu3Sn lattice toward the reaction front significantly faster than tin atoms diffuse inward toward the copper bulk.

This differential atomic flux produces a net deficit of matter on the copper side of the interface, generating high concentrations of lattice vacancies.

Vacancies coalesce into microscopic cavities once local supersaturation thresholds are crossed. These Kirkendall voids aggregate along the interface between the parent copper leadframe and the Cu3Sn intermetallic band. The resulting planar void arrays strip the mechanical attachment of its shear strength, transforming a metallurgical bond into a perforated failure boundary.

Solder joints formed over void-rich interfaces detach under minimal mechanical shock and standard operational vibration.

Substrate purity dictates the rate of Kirkendall void aggregation within copper leadframe interfaces. Leadframes containing trace impurities, specifically zinc, sulfur, phosphorus, and oxygen, demonstrate elevated void aggregation kinetics during 125 degrees Celsius baking cycles. Impurities segregate to grain boundaries, acting as heterogeneous nucleation sites that stabilize and cluster migrating vacancies.

High-purity oxygen-free copper substrates suppress void coalescing, maintaining interface integrity across extended thermal exposure.

Internal package interconnects face parallel diffusion hazards during sustained thermal baking. Internal gold wire bonds attached to aluminum die metallization pads undergo rapid atomic exchange at 125 degrees Celsius, creating Au-Al intermetallic compounds. Gold diffuses into aluminum faster than aluminum enters gold, generating extensive Kirkendall voiding beneath the wire ball bond periphery.

This degradation mechanism, coupled with the brittle AuAl2 intermetallic phase, produces bond shearing and electrical opens during package qualification testing.

Switching internal wire bond metallurgy directly impacts these solid-state degradation rates. Copper wire bonding over aluminum die pads features higher activation energies, reducing diffusion velocities and suppressing void generation during 125 degrees Celsius bakes. Copper-aluminum systems experience minimal phase progression over typical 96-hour drying cycles.

Specifying copper or palladium-coated copper wire bonds protects internal sensor die interconnects from thermal bake degradation.

Aperture

Can SMT Lines Recover Degraded Component Terminations?

SMT manufacturing facilities cannot reverse solid-state intermetallic growth through standard line adjustments once consumption reaches the plating surface. Production teams encountering sluggish solder wetting often attempt process compensation by altering the stencil printing configuration. Increasing stencil aperture volume deposits excess flux and SAC305 paste onto component lands.

While excess flux vehicles supply momentary protection against re-oxidation, unreacted intermetallics still yield unacceptable contact angles exceeding 55 degrees, producing defective solder fillets under IPC-A-610 criteria.

Stencil designs require modification when placing components that have undergone extended thermal dry baking. Standard aperture aspect ratios matching IPC-7525 guidelines yield insufficient solder heights over aged terminations displaying partial intermetallic emergence. Production engineers implement specific stencil aperture modifications to manage wet-out challenges:

• Home-plate aperture rounding reduces paste collection at corner margins while driving core paste volumes beneath bottom-terminated component pads.
• Aperture overprinting strategies extend the solder brick beyond the copper land pattern by 0.05 to 0.10 millimeters to supply active flux directly to the lead toe fillets.
• Step-up foil topologies elevate stencil thickness from 0.100 millimeters to 0.127 millimeters locally above critical sensor locations to maximize total flux deposition.
• Micro-slot venting patterns prevent volatile outgassing from trapping paste flux bubbles beneath leadless sensor packages during peak liquidus exposure.

Solder paste selection plays an active role in soldering performance over thick intermetallic layers. Standard no-clean formulations containing ROL0 flux activators carry insufficient acid numbers to strip passivation films from oxidized Cu6Sn5 and Cu3Sn surfaces. Switching to higher activity ROL1 or water-soluble ORH1 pastes improves wetting dynamics over partially consumed terminations.

Water-soluble chemistries mandate in-line wash operations, introducing assembly costs and mechanical wash hazards to open-cavity MEMS sensor assemblies.

Reflow thermal profile configuration must account for altered terminal wettability. Raising peak temperatures from 240 degrees Celsius to 255 degrees Celsius accelerates intermetallic dissolution into molten SAC305, temporarily assisting fillet formation. Extended time-above-liquidus profiles running beyond 75 seconds risk excessive dissolution of the underlying nickel barrier layer.

This over-reflow dissolves the barrier metallization completely, producing brittle quaternary intermetallics and cratering failure under the component pad.

Audit

Incoming inspection procedures must detect intermetallic growth before degraded components enter automated surface mount feeders. Standard visual inspection at 40x magnification cannot distinguish pure electroplated matte tin from an advanced Cu6Sn5 intermetallic front that remains sub-surface. Quality organizations apply specialized analytical tools to assess metallurgical integrity following supplier dry bakes or internal baking operations.

1. Cut component terminations cleanly using a diamond wafering saw set to low-speed operation to prevent mechanical smearing across soft tin interfaces.
2. Cast terminations inside cold-curing epoxy resin under vacuum backfill to fill microscopic edge voids and preserve perimeter intermetallic structures.
3. Grind the metallographic mount using silicon carbide papers stepped progressively from 400 to 2000 grit under constant liquid lubrication.
4. Polish the cross-section surface with diamond suspensions down to 0.05-micrometer colloidal silica to produce a scratch-free metallurgical interface.
5. Etch the mount lightly with a 2-percent ammonium persulfate solution to reveal intermetallic phase morphology and differentiate Cu6Sn5 from parent copper.
6. Measure remaining free tin thickness across ten standardized field locations using scanning electron microscopy backscatter electron imaging at 5000x magnification.

Wet balance testing per IPC J-STD-002 establishes pass-fail criteria for baked terminations by recording wetting force over time.

Wetting balance testing provides quantitative functional verification of termination solderability per J-STD-002 test standards. The instrument dips component terminations into a molten SAC305 solder bath held at 245 degrees Celsius while high-precision load cells track wetting force dynamics. Unbaked parts reach positive wetting force within 1.0 second, with maximum meniscus pull exceeding 0.20 millinewtons per millimeter.

Terminations carrying deep intermetallic degradation display delayed wetting times past 2.5 seconds, while severely oxidized terminations produce sustained negative forces indicating complete solder repulsion.

X-ray fluorescence plating thickness gauges deliver rapid non-destructive screening across production sample lots. Calibrated multi-layer XRF instruments separate bulk tin responses from underlying copper and nickel signals. Advanced XRF algorithms calculate the equivalent thickness of pure tin alongside the intermetallic boundary layer.

A measured free tin reserve below 1.50 micrometers triggers lot holds and blocks inventory release to surface-mount pick-and-place lines.

Procurement contracts protect sourcing lines by bounding component thermal history within clear specification limits. Component purchase agreements must cap permissible distributor bake cycles to a single compliant reset. Purchase agreements require distributors to deliver explicit thermal logging certificates displaying continuous oven temperature data and cumulative dwell duration for all dry-pack shipments.

Missing bake records or ambiguous component packaging dates warrant immediate shipment rejection before parts hit factory stock.

Supplier technical agreements covering bottom-terminated sensors and fine-pitch components must specify barrier metal stack-ups. Sourcing engineers eliminate leadframe degradation risks by mandating a minimum 2.00-micrometer electrolytic nickel underplate beneath pure matte tin finishes. This nickel diffusion barrier prevents direct copper-tin atomic exchange, allowing parts to endure multiple dry-pack bake cycles without losing solderability.

Component purchase orders lacking strict underplate specifications expose factory operations to unpredictable terminal degradation and assembly yield loss.

The vendor typically claims that baking parts for 96 hours at 125 degrees Celsius maintains full solderability compliance because the total remaining tin layer meets the catalog thickness specification.