Quantifying Long Term Thermal Hysteresis and Drift Sensitivity in Plastic Packaged Sub Bandgap References

Mold

Plastic encapsulation exerts continuous compressive stress on encapsulated silicon through chemical cure shrinkage and differential thermal contraction. Thermoset epoxy resins cure at temperatures between 165°C and 175°C. As the polymer chains cross-link, the compound shrinks volumetrically by 0.15 percent to 0.25 percent before cooling begins. Cooling the assembled leadframe to ambient temperature introduces mechanical force because the coefficient of thermal expansion for silica-filled epoxy spans 10 to 14 ppm/K, whereas silicon expands at 2.6 ppm/K and copper leadframes expand at 16.5 ppm/K. The contraction mismatch leaves the silicon die under planar compressive stresses between 50 MPa and 120 MPa at room temperature.

Moisture sorption disturbs this mechanical equilibrium across normal operating life. Epoxy matrices absorb atmospheric water vapor through capillary action, expanding the polymer network and relieving a portion of the original cure compression. Saturated plastic packages exhibit a reduction in die surface stress of 15 MPa to 30 MPa relative to a dry state.

Subsequent thermal cycling or operational heat drives this moisture out, reversing the expansion and returning the silicon to higher compressive levels.

Ambient humidity fluctuations alter encapsulant volume sufficiently to produce reversible reference output shifts of 120 parts per million in unshielded plastic packages.

Package geometry controls the magnitude of stress transmitted across the die surface. Miniature outline forms concentrate stress gradients near the die edges and corners, while larger packages distribute load more evenly across a thicker leadframe pad.

• Glass transition temperature defines the threshold where the encapsulant coefficient of thermal expansion increases by a factor of three, shifting mechanical pressure curves sharply above 140°C.
• Filler loading fraction controls both the modulus and moisture uptake, where an 88 percent spherical silica fill lowers total shrinkage at the expense of higher package stiffness.
• Die attach fillet height sets the perimeter shear distribution, with inconsistent wet-out driving asymmetric warping across the active collector junctions.
• Leadframe paddle thickness balances thermal dissipation against mechanical rigidity, where stamped 0.15 mm copper carriers deflect significantly more than etched 0.25 mm alloy alternatives.

Epoxy swelling alters die curvature. Incomplete cure cycles exacerbate the instability by allowing unreacted monomers to cross-link during prolonged heat exposure in the end installation. When assembly lines run shortened post-mold cure cycles below the four-hour standard, the uncured polymer chains undergo secondary polymerization over the initial 500 operating hours.

This secondary shrinkage increases normal compressive force by 10 MPa to 25 MPa, generating a permanent downward drift in reference potential that cannot be calibrated out at the board level.

Overlooking package stress mechanics produces precision analog sub-assemblies that fail multi-year field accuracy guarantees, forcing expensive board replacements and warranty claims across industrial deployment cycles.

Piezoresistance

Mechanical stress alters the electrical parameters of silicon through the piezoresistive effect, shifting resistivity and junction potentials within analog circuits. Sub-bandgap reference topologies operate below the standard 1.205 V silicon bandgap, relying on current-mode summing networks or sub-threshold field-effect transistors to generate stable potentials between 0.2 V and 1.0 V. These low-headroom cores sum a proportional-to-absolute-temperature voltage with a complementary-to-absolute-temperature base-emitter potential across matched bipolar pairs. The base-emitter voltage depends on the saturation current, which is an explicit function of intrinsic carrier concentration and minority carrier mobility within the base region.

Compressive stress lifts valence band degeneracy and splits conduction band valleys. This band deformation shifts majority and minority carrier mobility, altering the saturation current of the bipolar junctions. The base-emitter voltage of a vertical NPN transistor exhibits a stress sensitivity governed by the piezojunction coefficients, yielding a temperature-dependent offset.

Symmetrical layouts cannot cancel these errors when stress gradients cross the die unevenly. Copper leadframes induce compressive stress.

A planar compressive stress shift of 10 MPa across a sub-bandgap core alters the base-emitter potential by approximately 75 microvolts at room temperature.

Why Do Sub Bandgap Cores Shift?

Differential pairs designed to generate the proportional thermal component depend on precise current density ratios between adjacent emitters. Sub-bandgap circuits typically run collector current ratios of 1:8 or 1:16. Because piezoresistive coefficients vary with crystal direction on standard (100) silicon wafers, stress oriented along the axis modulates the emitter area efficiency asymmetrically.

The resulting discrepancy introduces a shift in the thermal slope, degrading the calibrated temperature curvature.

Resistor networks within the summing amplifier chain experience concurrent resistance changes. Diffused or polysilicon resistors exhibit piezoresistive gauge factors ranging from minus 30 to plus 70, depending on doping concentrations and dopant species. Thin-film silicon-chromium or nickel-chromium resistors offer lower gauge factors near 2 to 5, providing greater immunity to packaging stress.

Current-mode sub-bandgap architectures convert junction potentials into current through these resistors before summing into an output load resistor. Unmatched stress coefficients between resistor legs directly distort the programmed reference potential.

Die layout geometry dictates mechanical vulnerability. Placing the sub-bandgap core at the geometric center of the silicon die minimizes exposure to high shear stresses that peak at the die perimeter. Orienting the critical quad-cell bipolar pairs along the axes rather than the traditional cleavage planes reduces the piezoresistive shear sensitivity factor π44 to near zero.

Sub-bandgap architectures relying on CMOS transistors biased in weak inversion suffer additional drift through mechanical modulation of the gate oxide surface potential and carrier trap states. The drain current in weak inversion scales exponentially with the surface potential, converting subtle package deflections into measurable output fluctuations.

Thermal gradients skew internal matching. The spatial layout of active components around the reference core creates localized heat paths during operation. When power dissipation fluctuates within adjacent driver circuits on the same silicon substrate, asymmetric thermal expansion establishes dynamic stress gradients across the precision pairs.

The internal compensation loops cannot differentiate between these localized mechanical strain variations and genuine ambient temperature changes, resulting in transient reference deviations that track system computational load.

Silicon fractures under uncontrolled shear. Manufacturers defend the observed shifts by stating that standard automated test equipment measures parts only under steady-state factory conditions, leaving mechanical package interactions as application-specific phenomena outside datasheet limits.

Cycling

Temperature excursions produce closed-loop and non-closing output deviations defined as thermal hysteresis. Exposing a plastic packaged sub-bandgap reference to a thermal range from minus 40°C to 125°C alters the molecular structure of the molding compound. Above the glass transition temperature, polymer chains disentangle and slide past one another to accommodate thermal expansion.

Upon cooling back to 25°C, the chains freeze into altered configurations, failing to restore the initial spatial orientation. This structural relaxation manifests as an offset in the residual stress delivered to the silicon core.

A standard industrial thermal excursion from 25°C up to 125°C and down to -40°C leaves a median non-closing offset of 180 parts per million in molded SOT-23 packages.

Surface-mount solder reflow imposes the most severe mechanical shock during product fabrication. Peak temperatures reaching 260°C vaporize internal moisture within hours of board assembly, while the molten lead-free solder relaxes existing leadframe tension. As the assembly cools below the 217°C eutectic point of SAC305 alloy, the rigid solder joint locks the circuit board CTE mismatch directly to the reference package pins.

Post-reflow settling requires hundreds of hours at ambient conditions before the reference potential stabilizes within factory margins.

Quantifying the thermal hysteresis envelope demands a strict measurement sequence:

1. Bake the assembled boards at 125°C for 24 hours to eliminate residual moisture and dry the plastic encapsulant.
2. Stabilize the test assemblies inside a precision liquid-immersion or forced-air chamber at exactly 25°C for four hours.
3. Log initial reference potentials using an eight-and-a-half digit multimeter configured with ten-line-cycle integration.
4. Ramp the environmental chamber down to minus 40°C at a rate of 1°C per minute and soak for two hours.
5. Ramp the chamber up to 125°C at the same rate and soak for two hours to reach complete equilibrium.
6. Return the chamber to 25°C at 1°C per minute, soak for four hours, and capture the final stabilization voltage.

Reflow peak temperatures reach 260°C. Solder alloy choice dictates relaxation. High-temperature operating life tests per JESD22-A108 quantify long-term drift by operating devices at 125°C for 1,000 hours. The primary mechanism driving this permanent drift is the densification of the epoxy compound through continued thermal curing, coupled with chemical oxidation of the polymer backbone.

As the mold compound shrinks over months of high-temperature service, planar compressive stress increases monotonically. This compressive creep produces a unidirectional drift that tracks the logarithm of operating time, following a characteristic slope between 20 ppm and 80 ppm per square-root thousand hours.

JEDEC standard JESD22-A104 condition G specifies component level endurance under thermal cycling, stipulating that reference voltage shifts exceeding the published operational accuracy band void supplier compliance covenants.

Firmware

Digital compensation schemes attempt to linearize reference drift across operational lifetimes. Modern sub-bandgap components frequently incorporate on-chip EEPROM or non-volatile registers accessed over I2C or SPI buses to permit post-packaging calibration. Factory calibration trims the output voltage at a single ambient temperature point, nulling out the initial stress offset induced by mold cure and wire bonding.

When the part experiences subsequent thermal cycling on the target application board, the mechanical stress state diverges from the factory calibration state, reintroducing systemic errors that firmware algorithms must manage.

Firmware-driven lookup tables require localized board temperature readings to apply polynomial corrections. Because the thermal hysteresis loop is non-monotonic and path-dependent, the reference voltage at 25°C differs depending on whether the system arrived from an elevated operating temperature or a sub-zero cold soak. A static temperature lookup table fails to capture this historical path dependency, leaving residual errors up to 150 ppm uncorrected.

What Governs Register Level Trim Retention?

Non-volatile memory cells embedded alongside sub-bandgap cores suffer from mechanical charge leakage under stress. Floating gate structures and charge-trap oxides alter their tunneling barriers when package shear distorts the underlying silicon lattice. Stress relaxation over 1,000 hours at high operating temperatures can cause marginal memory cells to lose trim states, resulting in abrupt register alterations.

Sourcing teams avoid parts lacking parity bits and error-correcting code in their digital configuration maps.

Implementing effective host compensation involves systematic interface rules:

• Path tracking filters record the highest and lowest temperatures experienced since power initialization to estimate the hysteresis direction.
• Periodic ratiometric cross-checks compare the sub-bandgap output against a secondary on-board reference to detect sudden stress jumps.
• Write-lock sequencing prevents unintentional register updates caused by bus noise during heavy switching transients on shared I2C traces.
• Staged coefficient loading restores calibrated trim values from protected external system flash whenever cyclic redundancy checks fail.

Host polling introduces bus jitter. Communication lines routed across the circuit board introduce electrical noise into sensitive reference pins. The I2C bus clock and data lines run with transition rates that couple capacitive energy into the high-impedance nodes of sub-bandgap operational amplifiers.

Sourcing specifications stipulate isolated ground returns and minimum physical separations between digital serial traces and the analog output terminal to prevent digital communication from shifting the analog operating point.

How can predictive algorithms mathematically model the chaotic relaxation of random polymer networks across a decade of unpredictable field thermal variations?

Margin

Precision error budgets in industrial and medical instrumentation determine whether a design can utilize low-cost plastic packaging or must transition to hermetic ceramic housings. A sub-bandgap reference in a plastic SOT-23 or DFN package costs between 0.40 and 1.20 dollars in 10,000-unit volumes. The same internal silicon element packaged in an eight-terminal hermetic ceramic leadless chip carrier ranges from 6.00 to 18.00 dollars.

Sourcing teams evaluate whether board-level layout techniques can mitigate plastic package stress sufficiently to avoid the ceramic price penalty.

Isolation routing provides mechanical decoupling without altering bill-of-materials costs. Milling mechanical slots or router grooves around three sides of a surface-mount reference package interrupts the transmission of circuit board flexure stress into the component solder joints. A standard four-layer FR4 board exhibits an effective thermal expansion coefficient between 14 and 18 ppm/K. As the host assembly flexes under chassis mounting torque or environmental thermal expansion, the board transfers bending moments through the solder pads directly to the package bottom.

Router slots reduce board-induced strain transmission by up to 70 percent.

Board cutouts isolate trace distortion. Component placement rules dictate locating the precision reference near the center of the printed circuit board, oriented parallel to the shortest board edge to minimize bending radius exposure. Solder land patterns follow minimal-aperture guidelines to prevent solder volume disparities beneath gull-wing leads from tilting the package during surface-mount reflow.

Uneven solder fillets create asymmetric static loads that permanently alter reference output calibration. Yield drops when tolerances tighten.

Price scales with package stability. Sourcing strategies depend on rigorous total-cost-of-ownership modeling. Implementing board routing cutouts, sacrificial keep-out zones, and firmware calibration algorithms incurs fixed engineering overhead during development.

When production volumes exceed 50,000 units annually, the engineering investment required to stabilize plastic packages yields significant bill-of-materials savings compared to committing the product architecture to ceramic alternatives.

Mechanical stress on silicon relaxes under steady temperatures while stiffening under continuous cycling.