Common Centroid Transistor Layout Strategies for Low Drift Bandgap Cores
Common centroid transistor layouts for bandgap cores cancel linear thermal and lithographic gradients, reducing post-packaging output drift below 5 ppm per C.
Cross Quad Layout
Spatial Arrangement
Differential transistor pairs are positioned in a two by two matrix to cancel the effects of linear thermal and stress gradients across a silicon die. A cross quad layout places diagonally opposite components in parallel to ensure that the average center of the device remains constant. This configuration is essential for high precision analog circuits that require minimal offset voltage and long term stability.
Gradient Mitigation
Thermal variations from nearby power sources create non uniform temperatures across the surface of the chip. By employing a cross quad layout, an engineer ensures that a gradient affecting one side of the pair is offset by the same gradient affecting the other. This cancellation reduces offset voltage drift.
Stress Sensitivity
Piezoresistive effects in silicon alter the electrical characteristics of transistors based on their orientation and position relative to the package edge. The cross quad layout distributes these mechanical stresses equally among the active elements. Resulting measurements show a measurable reduction in common mode errors compared to linear placements.
Silicon Area
Designers trade increased routing complexity and larger area for the superior matching provided by this technique. Parasitic capacitance increases. Proper signal routing must maintain symmetry to preserve the benefits of the physical placement.