Modeling Viscoelastic Mold Compound Relaxation and Board Flexure Coupling in Automotive Bandgap References

Stress

Precision analog reference circuits rely on the temperature dependence of base-emitter junction voltages to generate an output immune to supply variations. When encapsulated in thermosetting polymer packages, the underlying silicon crystal experiences mechanical forces exerted by the surrounding package materials. These mechanical forces alter the electrical characteristics of the integrated devices through piezoresistive coupling, shifting the output voltage from its nominal trimmed state.

In automotive applications operating across temperature spans from -40°C to 150°C, these stresses evolve continuously over time and operational cycles.

Piezoresistive Coupling Mechanics in Junction Voltages

Base-emitter potential drops (V_be) and differential base-emitter potentials (ΔV_be) depend directly on minority carrier mobility and intrinsic carrier concentration. An applied mechanical force distorts the silicon crystal lattice, altering the conduction band minima and valence band sub-band energies. This band edge shift changes the effective mass of charge carriers, altering mobility (μ_n and μ_p) and modifying the intrinsic carrier concentration (n_i).

In a standard Brokaw or Wildar bandgap architecture, the output voltage combines a complementary-to-absolute-temperature V_be component with a proportional-to-absolute-temperature ΔV_be component multiplied by a gain factor N.

Die strain alters carrier mobility directly. When compressive or tensile stress acts upon the active bipolar transistors forming the bandgap core, the fundamental balance between V_be and ΔV_be changes. Uncompensated mechanical loads produce a parametric shift in the reference voltage that cannot be distinguished from thermal drift by downstream processing circuitry.

This mechanical-to-electrical transduction mechanism creates long-term output drift in automotive electronic control units.

• Valence band degeneracy lifting shifts heavy and light hole effective masses, altering the intrinsic carrier concentration n_i and inducing offset drift in pnp transistor pairs.
• Mobility anisotropy in n-doped wells redistributes current densities across multi-collector structures, degrading the current gain ratio matching between reference branches.
• Piezojunction effect on saturation current alters reverse saturation current I_s exponentially with normal force components, generating a non-linear voltage shift across operating temperature extremes.
• In-plane normal force imbalances induce differential base-emitter offsets between cross-coupled quad transistor layouts, eroding initial laser trimming accuracy.

Tensor Components across Silicon Crystallographic Planes

Anisotropy governs how mechanical forces alter electrical properties within a single-crystal semiconductor lattice. The relationship between the fractional change in resistivity (Δρ/ρ₀) and the six independent stress tensor components (σ_xx, σ_yy, σ_zz, τ_yz, τ_xz, τ_xy) is represented by piezoresistive coefficients (π_ij). For standard (100) silicon wafers oriented with primary flat along the direction, the in-plane normal stresses (σ_xx and σ_yy) and in-plane shear stress (τ_xy) dominate the total electrical shift.

For p-type resistors and pnp transistor emitters, the piezoresistive response along the principal wafer axes simplifies through tensor transformation:

Δρ_xx / ρ₀ = π₁₁′ σ_xx + π₁₂′ σ_yy + π₁₃′ σ_zz

where the transformed coefficients for a alignment relate to the fundamental crystallographic coefficients according to:

π₁₁′ = 0.5 · (π₁₁ + π₁₂ + π₄₄)

π₁₂′ = 0.5 · (π₁₁ + π₁₂ – π₄₄)

In p-type silicon, π₄₄ exhibits a large positive magnitude (+138.1 × 10^-11 Pa^-1), whereas π₁₁ and π₁₂ remain relatively small (+6.6 × 10^-11 Pa^-1 and -1.1 × 10^-11 Pa^-1 respectively). Consequently, shear stresses and normal stress differences along exert maximum influence over p-type device matching. Silicon exhibits anisotropic piezoresistive coefficients.

In n-type collector and emitter regions, π₁₁ dominates (-102.2 × 10^-11 Pa^-1), making n-type devices highly sensitive to direct normal stresses aligned with the crystal axes.

Uncompensated package forces convert mechanical board deflection into direct voltage drift in automotive bandgap references.

Neglecting piezoresistive tensor coupling during layout definition leads to bandgap output drift that exceeds AEC-Q100 Grade 0 drift limits during thermal cycling.

Decay

Thermosetting polymers used in IC packaging undergo time-dependent physical changes after mold solidification. Epoxy Mold Compounds (EMC) consist of cross-linked epoxy resins heavily loaded with fused silica fillers (typically 80% to 90% by weight) to match the coefficient of thermal expansion (CTE) of the silicon die and copper leadframe. Despite high filler loadings, the polymer matrix retains viscoelastic properties.

Upon completion of post-mold cure and reflow soldering, the compound traps residual stresses caused by CTE mismatches between package constituents. Over time and under thermal exposure, these trapped stresses relax as the polymer chains slowly reorganize.

Prony Series Formulation for Mold Polymer

Viscoelastic response in epoxy encapsulation materials is mathematically captured through a linear combination of exponential relaxation modes. The time-dependent shear modulus G(t) or Young’s modulus E(t) is modeled using a Generalized Maxwell formulation expressed as a Prony series:

E(t) = E_&infty; + ∑_i=1^N E_i · exp(-t / τ_i)

where E_&infty; represents the fully relaxed long-term equilibrium modulus, E_i represents the relaxation strength of the i-th Maxwell element, and τ_i denotes the characteristic relaxation time associated with that element. The relaxation times span multiple orders of magnitude, capturing rapid initial stress relief immediately following reflow alongside gradual long-term creep occurring over thousands of operating hours.

Temperature Dependence and Shift Factor Equations

Time-temperature superposition allows long-term material behavior to be projected from short-term mechanical testing at elevated thermal states. The temperature-dependent shift factor a_T scales the relaxation times τ_i according to the operational temperature environment T. Near the glass transition temperature (T_g) of the epoxy mold compound, the Williams-Landel-Ferry (WLF) equation models the shift factor:

log₁₀(a_T) = -C₁ · (T – T₀) /

where T₀ is the reference glass transition temperature, and C₁ and C₂ are empirically derived material constants. At temperatures significantly below T_g (typically below T_g – 15°C), the material behavior transitions to an Arrhenius formulation governed by an activation energy E_a:

ln(a_T) = (E_a / R) ·

Thermal cycles accelerate polymer creep. As the automotive control unit cycles between high-ambient engine compartment temperatures (125°C to 150°C) and cold soak states (-40°C), the viscoelastic relaxation rate varies continuously. During high-temperature dwell periods, mold compound relaxation releases compressive stress on the silicon die face.

When the package returns to room temperature, the residual stress equilibrium is permanently altered, shifting the baseline bandgap voltage output.

High glass transition temperature mold materials minimize long-term voltage drift by stabilizing the polymer network above ambient operational limits.

Packaging vendors frequently maintain that post-mold cure relaxation falls within standard parametric variation and requires no individual lot-level mechanical characterization.

Bend

Printed circuit boards installed in automotive electronic control units experience mechanical loading from housing assembly and thermal expansion mismatched components. Flexural deflection of the board substrate transfers strain through the solder joints and package leads directly to the encapsulated silicon die. In precision bandgap references, board bending acts as an external mechanical signal that modulates electrical output voltage independently of thermal or electrical inputs.

Strain Transfer across Solder Interconnects

Flexural force applied to a circuit substrate propagates through copper traces, solder joints, and package leadframes to reach the active silicon face. The mechanical strain transmission efficiency depends on the package geometry, leadframe compliance, die-attach adhesive modulus, and solder joint array topology. Solder fatigue alters load transmission.

Standard leaded surface-mount packages such as SOIC or TSSOP utilize compliant gull-wing leads that flex under board deformation, isolating the die from a significant fraction of board-level strain. Conversely, Quad Flat No-Lead (QFN) packages, Wafer Level Chip Scale Packages (WLCSP), and Land Grid Arrays (LGA) establish rigid mechanical coupling between the PCB and the die.

• Substrate thickness scaling dictates flexural rigidity, where a doubling of PCB thickness increases bending stiffness by a factor of eight and elevates strain transmission to surface-mounted components.
• Solder joint alloy creep relaxes initial assembly strain over time, converting elastic displacement into inelastic plastic deformation that continuously shifts the mechanical baseline.
• Exposed pad solder coverage anchors the die paddle directly to board copper, maximizing strain transmission compared to un-flooded thermal voids.
• Distance from mounting chassis bosses dictates the localized bend radius under structural enclosure deflection, establishing high strain gradients near retention screws.

Board Substrate Deflection in Automotive Assemblies

Four-point fixture testing establishes controlled curvature across the component mounting area to evaluate electrical sensitivity under displacement. In an assembly subjected to bending, the strain at the board surface (ε_board) couples to the silicon die through a strain transmission ratio (γ = ε_die / ε_board). Leadframe thickness shifts internal tension.

The strain field induced across the die surface is not uniform; high shear stresses concentrate near the package corners and exposed pad boundaries.

Packaging geometry dictates mechanical gain. In a QFN package with an exposed thermal pad soldered to a 1.6 mm FR4 board, flexure induces substantial in-plane stresses (σ_xx and σ_yy) directly inside the bandgap core. These flexure-induced stresses superimpose on the existing viscoelastic mold compound stress field.

The total stress acting on the silicon is the sum of the time-decaying viscoelastic molding stress and the dynamic mechanical flexure stress imposed by the board assembly.

Compliance with IPC-9701 bend testing mandates that electrical reference parameters remain within specification limits across two thousand flexure cycles.

Failure to meet the IPC-9701 flexure limits invalidates the vehicle control unit qualification under ISO 26262 functional safety audits.

Matrix

Comprehensive modeling requires converting three-dimensional stress fields from finite element meshes into localized piezoresistive circuit variations. Standard SPICE simulators cannot natively evaluate mechanical strain fields without custom sub-circuit modeling or parameter mapping. To evaluate bandgap performance under coupled viscoelastic relaxation and board flexure, a sequential co-simulation framework bridges the structural domain and the electrical circuit domain.

Finite Element Extraction to Circuit Simulation

Structural solver nodes at the silicon active surface yield normal and shear stress vectors under thermo-mechanical load cases. The numerical co-simulation methodology follows an automated data extraction and transformation sequence:

1. Perform three-dimensional meshing of the packaged integrated circuit mounted on a multi-layer FR4 test board using solid continuum elements.
2. Apply viscoelastic material properties to the mold compound using Prony series parameters obtained from dynamic mechanical thermal analysis.
3. Execute sequential thermo-mechanical loading steps covering reflow cooling, post-mold cure storage, room temperature assembly, and 4-point board bending.
4. Extract stress tensor profiles (σ_xx, σ_yy, σ_zz, τ_xy) across the exact spatial coordinates of the bandgap core layout.
5. Calculate localized piezoresistive resistivity variations for each individual transistor, resistor, and current mirror branch in the reference topology.
6. Inject modified mobility, saturation current, and resistance parameters into SPICE electrical models to evaluate net bandgap output voltage drift.

Consider a representative automotive bandgap circuit where the core reference voltage depends on a pnp transistor pair (Q₁ and Q₂) operating at a 1:8 emitter area ratio, paired with p-type diffusion resistors (R₁ and R₂) establishing the gain factor N = R₂ / R₁. Unpassivated dies suffer direct shear. Assume an initial finite element analysis indicates that reflow cooling followed by 500 hours of room-temperature aging produces an in-plane normal stress σ_xx = -85 MPa and σ_yy = -110 MPa at the core location.

When the host PCB undergoes 4-point flexure, an additional tensile strain imparts Δσ_xx = +35 MPa and Δσ_yy = +10 MPa.

The net stress tensor components acting on the silicon crystal become:

σ_{xx, net} = -85 + 35 = -50 MPa

σ_{yy, net} = -110 + 10 = -100 MPa

σ_diff = σ_{xx, net} – σ_{yy, net} = +50 MPa

Piezoresistive Coefficient Mapping in SPICE Models

Circuit simulators evaluate bandgap stability by modifying model parameters through user-defined behavioral equations representing stress dependency. In pnp bipolar transistors, the saturation current I_s shifts in response to stress according to:

I_s(σ) = I_s0 · exp

where C_π and D_π are empirical piezojunction coefficients derived from hydrostatic and uniaxial stress measurements (typically C_π ≈ -1.2 × 10^-10 Pa^-1 and D_π ≈ +2.5 × 10^-10 Pa^-1 for pnp structures). Simultaneously, the gains of the p-type feedback resistors R₁ and R₂ shift based on their orientation relative to the axis:

ΔR₁ / R₁₀ = π₁₁′ σ_{xx, net} + π₁₂′ σ_{yy, net}

Assuming R₁ is oriented along (π₁₁′ = +71.8 × 10^-11 Pa^-1 and π₁₂′ = -66.3 × 10^-11 Pa^-1), the fractional resistance change under the net stress state is calculated as:

ΔR₁ / R₁₀ = (71.8 × 10^-11) · (-50 × 10⁶) + (-66.3 × 10^-11) · (-100 × 10⁶)

ΔR₁ / R₁₀ = -0.0359 + 0.0663 = +0.0304 (or +3.04%)

If resistor R₂ is positioned orthogonally along the axis, its fractional resistance change follows the inverted coefficient mapping:

ΔR₂ / R₂₀ = π₁₂′ σ_{xx, net} + π₁₁′ σ_{yy, net}

ΔR₂ / R₂₀ = (-66.3 × 10^-11) · (-50 × 10⁶) + (71.8 × 10^-11) · (-100 × 10⁶)

ΔR₂ / R₂₀ = +0.03315 – 0.0718 = -0.03865 (or -3.87%)

The resistance gain ratio N = R₂ / R₁ shifts from its nominal value N₀:

N_new = N₀ · (1 – 0.03865) / (1 + 0.0304) ≈ N₀ · (0.96135 / 1.0304) ≈ 0.9330 N₀

This 6.7% shift in the gain factor N, combined with the exponential change in I_s across Q₁ and Q₂, shifts the generated bandgap voltage V_ref by several tens of millivolts. Such a magnitude far exceeds the typical 0.5% total accuracy window demanded by high-precision automotive analog-to-digital converters.

A 100 MPa compressive in-plane stress induces up to 1.8 mV of bandgap voltage drift at room temperature in standard quad-layout reference cores.

Whether sub-micron multi-layer passivations provide sufficient shear decouplers to negate mold polymer relaxation remains an active area of empirical investigation.

Shield

Engineers employ physical layout techniques, mechanical board modifications, and active circuit trim methods to isolate sensitive analog circuits. Mitigating viscoelastic relaxation and board flexure coupling requires an integrated approach spanning wafer layout, package selection, and PCB manufacturing rules.

Layout Topologies and Crystallographic Alignment

Symmetric common-centroid configurations cancel linear stress gradients across active die areas. Corner pin placements concentrate force. Placing sensitive pnp pairs in a cross-coupled quad arrangement (A-B-B-A) ensures that linear stress gradients across both the x-axis and y-axis affect both device pairs identically, preserving matched current densities.

Cross-quad layouts mitigate axial shear.

Orienting critical resistors and transistors along crystallographic directions with minimal piezoresistive coefficients reduces mechanical sensitivity. On (100) silicon, placing p-type resistors at a 45° angle relative to the primary wafer flat aligns them with the and crystallographic axes. Along these axes, the shear piezoresistive coefficient π₄₄ drops out of the in-plane equations, reducing overall strain sensitivity by up to 80% compared to standard placement.

Mechanical Isolation and Board Trench Specifications

Router cuts executed adjacent to component land patterns disrupt strain propagation paths within the board assembly. Milled slot trenches placed parallel to the component edges isolate the packaged IC from PCB flexure moments. Trench slots isolate substrate strain.

Standard design practices specify a slot width of 1.0 mm to 1.5 mm placed within 2.0 mm of the QFN or SOIC package edge, extending past the package corners by at least 3.0 mm to redirect stress lines away from the silicon die.

Dynamic temperature gradients skew differential pairs. Digital trim protocols performed after full board assembly correct for static stresses introduced by reflow soldering and initial mold cure. However, post-assembly trimming cannot compensate for dynamic board flexure occurring during vehicle operation or continuous viscoelastic relaxation over lifetime thermal exposure.

Combining 45° diagonal silicon layout alignment, high T_g mold compounds, and PCB router isolation slots provides a complete defense against thermomechanical reference drift. Temperature gradients skew differential pairs. Careful co-design of layout symmetry, package strain buffering, and board routing slots holds total automotive reference drift below 0.1 percent across the complete operational lifespan.