Allan Deviation Noise Floor Characterization in Delta Sigma Converters

Cadence

Precision digitizers running at continuous sample rates routinely present deceptive datasheet figures. A converter quoting 0.1 microvolts of root-mean-square noise across an output data rate of 10 samples per second yields that figure over a brief five-second observation interval. Extend that window to one hour, and the computed sample variance often increases tenfold.

Standard deviations calculated across static arrays bury the temporal structure of the error, treating low-frequency drift identical to thermal agitation. Instrumentation teams designing nanovolt balances, borehole seismometers, and downhole quartz pressure sensors encounter this failure during baseline settling trials.

Allan deviation addresses this divergence by computing variance over adjacent averaging intervals as a direct function of observation duration. Originating in cesium beam atomic clock stability measurement, the Allan variance isolates individual noise mechanisms by their mathematical slope on log-log plots. The algorithm collects a continuous time-series record, partitions the dataset into contiguous clusters of duration tau, calculates the mean of each cluster, and computes the sum of squared differences between adjacent clusters.

Sweeping tau across multiple decades transforms raw converter codes into an exact operational map of stability.

A zero-drift switched-capacitor converter at 25 degrees Celsius achieves an Allan floor of 18 nanovolts at an optimum averaging time of 42 seconds.

Averaging readings over time reduces uncorrelated noise. White thermal noise drops precisely along the square root of the averaging window. When the integration period extends past the transition threshold where one-over-f flicker noise equals white noise, further averaging yields zero noise reduction.

Pushing the averaging window deeper into thermal drift regimes steadily degrades effective resolution.

Signal acquisition across precision bridge topologies relies on defining this turning point with exact temporal boundaries. An engineer who knows the inflection duration configures hardware decimation registers and software finite-impulse-response filters to terminate integration before the drift boundary takes over. The instrument extracts the highest attainable signal-to-noise ratio without wasting compute cycles or accumulating ambient thermal wander.

Allan characterization converts a blind averaging guess into an analytical design parameter.

Aggressive oversampling combined with digital filtering provides optimal noise reduction only while the system operates to the left of the stability minimum.

Slope

Power spectral density calculations often disguise the boundary between distinct spectral noise processes due to windowing leakage and bin smearing at millihertz frequencies. The two-sample Allan variance maps these processes directly into distinct linear power-law gradients. By plotting Allan deviation against the observation time tau on logarithmic axes, the instrumentation specialist reads the physical origins of the converter noise floor like a diagnostic chart.

Each physical noise source in the converter signal chain imparts a specific signature to the Allan plot:

• Quantification noise generates a negative-one slope indicating that ultra-fast averaging suppresses high-frequency round-off errors at a linear pace.
• White thermal noise displays a negative-one-half slope signifying classic Gaussian distribution where fourfold averaging halves the uncertainty.
• Flicker noise forms a horizontal plateau with a zero slope where ongoing sample integration yields zero improvement in measurement precision.
• Random walk drift produces a positive-one-half slope tracing non-stationary mechanical creep, substrate stresses, and resistor thermal fluctuations.
• Linear temperature drift creates a steep positive-one slope documenting steady ambient shifts inside the enclosure.

The mathematical representation of Allan variance over a time series of digitized samples tracks through discrete equations. Let the digitized stream contain N discrete voltage readings taken at uniform sampling intervals tau-zero. Grouping the sequence into contiguous blocks of length m yields an averaged sequence where each block spans an observation window tau equal to m multiplied by tau-zero.

The two-sample Allan variance equals half the expected value of the squared difference between consecutive block averages. The Allan deviation is the square root of this value.

Evaluating this series over values of m spanning from unity to one-tenth of the total sample count maps the converter noise dynamics across decades of time. The lowest point on the resulting curve represents the absolute noise floor of the digitizer. This trough pinpoints the critical integration time tau-optimum.

Running a moving-average filter or decimation engine beyond tau-optimum degrades the precision of the output word.

Converting a voltage noise spectral density to an expected Allan floor demands calculating the white noise density e-sub-n in nanovolts per root hertz. For white Gaussian noise with a unilateral bandwidth B, the Allan deviation equals e-sub-n divided by the square root of two multiplied by tau. If an ultra-low-noise front end records 3.2 nanovolts per root hertz, the Allan deviation at a one-second window reaches 2.26 nanovolts RMS.

At four seconds, the deviation drops to 1.13 nanovolts.

The transition toward the flicker floor defines real hardware limits. Bipolar input stages exhibit low 1/f corner frequencies, often below 1 hertz, keeping the horizontal plateau depressed. Unchopped CMOS inputs suffer 1/f corners reaching into hundreds of hertz, elevating the Allan floor early.

The precise placement of tau-optimum depends on whether external environmental shifts intervene before internal device flicker dominates.

Whether unmodeled thermoelectric junctions on the PCB ground plane alter the Allan minimum before semiconductor flicker traps can dominate remains an empirical question for each board layout.

Chamber

Environmental stability determines whether a bench trial isolates true converter silicon performance or merely records air currents in the testing bay. An unprotected evaluation card sitting on an open laboratory bench responds to ambient heating cycles, human movement, and HVAC duct cycling. These external shifts generate thermal gradients across integrated circuit pins, introducing parasitic Seebeck voltages that masquerade as low-frequency converter noise.

Copper traces joining Kovar device leads form thermocouple junctions that generate approximately 40 microvolts per degree Celsius. Symmetric layout techniques cancel these voltages when thermal gradients across the board remain uniform. Unequal heating from a neighboring power regulator or linear drift in ambient air breaks that symmetry, generating nanovolt-level errors that inflate the Allan deviation at integration times exceeding ten seconds.

Thermal gradients exceeding five millikelvins per minute across input leads inject false random walk signatures into long-term converter datasets.

Capturing clean Allan deviation curves demands a rigorous isolation protocol:

1. Thermal mass buffering seals the device under test inside a solid aluminum enclosure weighing at least two kilograms to dampen rapid air temperature fluctuations.
2. Battery supply isolation powers the converter and its reference from sealed lead-acid or lithium iron phosphate cells to eliminate mains-frequency hum and common-mode transients.
3. Input short verification bonds differential analog inputs directly together through matched copper foil at the terminal block, preventing loop induction.
4. Continuous data logging captures raw conversion results without host-side decimation for a continuous run lasting at least seventy-two hours.
5. Chamber thermal soak stabilizes the environmental test chamber at a fixed temperature setpoint within 0.1 degree Celsius prior to initiating the capture array.

A typical scenario exposes the cost of sloppy bench containment. Take a 32-bit delta-sigma converter with a shorted input, operating at an internal digital filter rate of 50 samples per second. Over an unshielded 24-hour test, the laboratory HVAC cycling every 25 minutes imposes a cyclic oscillation on the data stream.

Computing Allan deviation on this polluted record introduces a severe hump between tau values of 300 seconds and 1,500 seconds, artificially raising the apparent noise floor by 14 decibels. The analyst incorrectly diagnoses this peak as internal silicon defect or reference diode instability, triggering unnecessary part respins.

Enclosing the same assembly inside an insulated metal box inside a thermal chamber flattens the curve out to 3,000 seconds. The genuine Allan floor surfaces at 12 nanovolts between tau values of 40 seconds and 120 seconds. Beyond 120 seconds, the curve climbs gradually with a plus-one-half slope, tracking the true aging and chemical drift of the board solder joints.

Bypassing thermal buffering during qualification invalidates the stability dossier, causing designers to reject acceptable converter lots and accept drifted ones.

Modulator

Delta-sigma conversion mechanics combine an oversampling analog modulator with an internal digital decimation filter. The analog modulator continuously shapes quantization noise, shoving spectral power out of the low-frequency baseband and upward into high frequencies. The digital decimation filter, typically a cascaded integrator-comb sinc structure, carves away high-frequency noise and downsamples the data to the final output word rate.

The interaction between modulator architecture and decimation filtering alters the time-domain Allan deviation plot.

Continuous-time delta-sigma topologies use passive or active RC integrators, providing inherent anti-aliasing against input transients. Discrete-time switched-capacitor topologies sample charge across discrete clock phases, offering superior transfer gain accuracy at the expense of sampling kickback currents. In high-resolution switched-capacitor modulators, clock jitter degrades the noise floor at higher baseband frequencies, but at sub-hertz regimes, low-frequency 1/f noise of the input differential pair controls performance.

Modulators incorporating continuous internal chopping push the white-noise Allan slope beyond one thousand seconds of integration time.

Internal chopping shifts the input signal and device 1/f noise to alternating phases, moving baseband flicker noise to the chopping frequency. The subsequent decimation filter rejects the modulation carrier. This dynamic offset cancellation depresses the Allan deviation floor, allowing the negative-one-half white noise slope to extend across long integration periods.

Chopping suppresses input stage offset drift from 100 nanovolts per degree down to less than 5 nanovolts per degree.

Yet internal chopping introduces fine trade-offs. The chopping switches inject charge into the source impedance, generating dynamic current pulses. If the signal source presents an impedance mismatch exceeding 1 kilohm, these charge pulses translate into input offset voltages that fluctuate with temperature.

The Allan curve then shows random walk divergence at shorter tau values than seen in unchopped modes.

Digital decimation filter selection also adjusts the shape of the Allan curve at short averaging intervals:

• Sinc1 decimation filters provide linear boxcar averaging, delivering rapid updates but inadequate rejection of modulator out-of-band noise, flattening the early curve.
• Sinc3 decimation filters eliminate second-order modulator quantization noise completely, ensuring the early Allan deviation matches the pure negative-one-half white noise slope.
• Sinc4 decimation filters generate high attenuation around integer multiples of the data rate, optimizing wideband reject bands at the cost of longer settling times.
• Fast-settling composite filters combine initial wideband acquisition with steep FIR post-filtering, creating minor ripples in the Allan deviation across low tau values.

Voltage reference stability governs the converter output as full-scale input levels are approached. With an analog input grounded, Allan deviation characterization exposes only the input amplifier and modulator baseline noise floor. Applying a full-scale DC input shifts the dominant noise mechanism to the reference path.

A standard buried Zener reference exhibits lower flicker noise floors than bandgap architectures, but consumes substantially higher supply power. Thin-film bandgap references achieve low initial tolerance, yet their sub-hertz 1/f noise causes the Allan floor to turn upward into drift at tau values below 10 seconds.

Fabrication teams routinely claim that integrated buffer amplifiers match the performance of bare modular dies, but real test records reveal those internal buffers raise the 1/f Allan floor threefold.

Procurement

Datasheet specifications for 24-bit and 32-bit converters conceal operational limitations beneath idealized bench headlines. Suppliers publish effective number of bits, noise-free counts, and input-referred RMS noise metrics captured over brief acquisition intervals. These figures document performance under ideal laboratory conditions over windows rarely extending beyond 100 milliseconds.

Sourcing engineers purchasing converters for long-dwell industrial metrology must quantify the true cost of identifying the long-term noise floor.

A factory qualification dossier omitting long-term Allan variance analysis forces the customer to assume all verification expenses. Qualifying a precision converter on a 72-hour burn-in trial consumes substantial chamber time. If an incoming inspection protocol requires testing 20 sample units from a 2,000-piece wafer lot across five decades of tau, the qualification sequence requires 1,440 chamber hours.

Testing costs quickly outstrip the purchase price of the bare silicon.

Procuring precision ADCs requires contractual agreement on stability test conditions. Purchase specifications must bind the vendor to definite low-frequency limits rather than dynamic audio metrics like total harmonic distortion. Standard testing criteria demand that the vendor define the Allan floor, the integration time tau-optimum, and the temperature coefficient of the noise floor across the operating temperature envelope.

Under international standard IEC 60751 for industrial instrumentation and IEEE standard 1057 for digitizing waveform recorders, stability characterization across specified averaging windows establishes baseline acceptance criteria. When purchase contracts specify compliance with IEEE 1057 Clause 4.6 for long-term drift and low-frequency noise floors, the vendor becomes legally accountable for thermal walkout, shielding the buyer against silent silicon substrate revisions that degrade precision.