Common Centroid Transistor Layout Strategies for Low Drift Bandgap Cores
Common centroid transistor layouts for bandgap cores cancel linear thermal and lithographic gradients, reducing post-packaging output drift below 5 ppm per C.
Efuse Calibration
Nonvolatile Adjustment
Permanent memory elements are blown during the final test phase to hard wire correction factors into an integrated circuit. During efuse calibration, a high current pulse creates a physical change in a metal or polysilicon link. This process stores digital coefficients that adjust the output of analog sensors or voltage references.
Correction Mechanism
Automated test equipment measures the raw output of a device and calculates the necessary offset. Once the efuse calibration completes, the internal logic applies these bits to a digital to analog converter. The circuit then maintains its calibrated state throughout its operational life.
Reliability
Resistance of the blown link must remain high enough to prevent accidental reconnection over time and ensure the permanent isolation of the bit. Engineers monitor the voltage levels required for efuse calibration to ensure that the physical rupture of the fuse is complete. Drift results from inadequate energy.
Production Flow
Trimming occurs after the silicon has been processed but often before the final packaging step. While efuse calibration removes the errors from manufacturing tolerances, it cannot account for the stresses introduced during the molding process. Modern designs often include a second bank of fuses for post assembly correction.