Planarization Process
Semiconductor wafer planarization combines chemical slurry etching with mechanical pad abrasion to yield uniform surface topography across patterned microelectronic layers. Chemical mechanical planarization removes excess deposited dielectric or metallic overburden following deposition steps such as copper electroplating or shallow trench isolation oxide deposition. Slurry chemistry reacts with the topmost topography to form an easily abraded passivation layer, which the rotating polishing pad selectively shears away at elevated features.
Material removal terminates once the underlying target layer is exposed across the wafer substrate, preventing severe topological steps that disrupt subsequent photolithography focus depth.
Removal Mechanism
Material removal rates depend directly on the relative velocity of the wafer carrier and the downward mechanical pressure applied across the polishing platen. Prestonian mechanical behaviour dictates that removal rates scale with the product of applied downforce and relative platen velocity. Chemical constituents in the liquid suspension alter surface atom binding energy, accelerating wear through oxidation or hydrolyzation without corroding low-lying recesses.
A polyurethane pad maintains roughness through periodic diamond conditioning to prevent glazing and sustain uniform slurry transport. Polishing kinetics cease to follow linear wear models once local fluid film pressure builds up, shifting wafer contact into hydrodynamic or boundary lubrication regimes.
Metrological Qualification
Optical interferometry and high-resolution spectroscopic reflectometry track residual layer thickness and planarity variations across the polished surface. Thickness uniformity metrics confirm that copper erosion and dielectric dishing remain within design rule tolerances over multi-pitch array regions. Defect inspection tools measure particle contamination, scratches, micro-voiding and surface haze across the polished wafer.
Non-uniform slurry distribution across large wafer diameters causes edge-to-centre thickness variation, requiring zoned carrier backpressure adjustment. High polishing friction causes thermal variations across the pad face that distort chemical removal rates if infrared pyrometric feedback loops fail.
Defect Boundary
Mechanical shearing forces during pad sweep introduce shearing stresses capable of shearing low-k dielectric stacks beneath metal interconnect levels. Sub-surface cracking and delamination occur if shear stress exceeds inter-layer adhesive strength. Over-polishing widens conductive metal line resistance variances by thinning copper wiring channels excessively.
Incomplete clearing leaves metallic bridges behind, producing functional electrical shorts between adjacent interconnect nodes. Dishing tolerances govern layout metal density rules, terminating acceptable polishing windows when pattern densities fluctuate past calibrated ranges.
