Die Attach Adhesive Coefficient Mismatch Mitigation in MEMS Accelerometers
Selecting low-modulus die attach adhesives with glass transition temperatures outside operating limits eliminates non-linear MEMS zero-g offset drift.
Capacitive Sense Fingers
Microcomb Geometry
Micromachined interdigital array structures form variable differential capacitors that transduce physical displacement into electrical charge variations across sub-micron air gaps. Silicon sensor designs incorporate capacitive sense fingers to detect displacement of proof masses in MEMS accelerometers and gyroscopes. The structural dimensions govern baseline capacitance and displacement sensitivity within the physical sensor cavity.
Operational limits are defined by the electrostatic pull-in voltage where opposing finger arrays snap into mechanical contact and cause electrical shorting across the differential array node.
Electrostatic Coupling
Differential capacitance changes proportionally with overlapping finger surface area and inversely with air gap distance. Deflection of capacitive sense fingers under inertial loading alters the balanced electrical charge distribution across differential readout channels. Switched-capacitor readout circuits convert these minute charge variations into a calibrated output voltage.
Parasitic Capacitance
Surrounding substrate silicon and metallization traces introduce fixed shunt capacitance that attenuates the differential signal ratio. Substrate grounding strategies reduce parasitic effects around capacitive sense fingers to preserve signal-to-noise performance. Guard rings placed around high-impedance sense nodes isolate the measurement signal from adjacent switching lines.
Etch Deviation
Deep reactive ion etching processes introduce sidewall taper angles that alter the nominal inter-finger gap width across the wafer die. Manufacturing variations alter capacitive sense fingers dimensions and create nominal offset voltage shifts before device calibration. Wafer-level testing measures baseline capacitance to calculate trim parameters for programmable capacitor arrays.