Optoelectronic Architecture
Multi-layered semiconductor devices that separate the light-sensing array from the processing circuitry are widely used in advanced imaging. The adoption of a stacked CMOS image sensor allows for higher processing speeds and improved pixel design by placing the photodiode layer directly on top of the logic circuit. This design reduces the silicon area required for each pixel while maximizing the light collection area.
The resulting sensor achieves both high frame rates and superior dynamic range.
Signal Integration
Pixel level connections between the sensor layer and the logic layer are made using through-silicon vias or direct wafer bonding. This layout allows for parallel readouts that process image data much faster than traditional planar sensors. The close proximity of the memory and logic circuits minimizes signal latency and power consumption.
Industrial Testing
Verification of the sensor performance involves testing the quantum efficiency and dark current across the entire temperature range. Calibration blocks with uniform light sources are used to evaluate pixel uniformity and detect any defective pixels.
Thermal Dissipation
Concentration of heat from the high-speed processing logic can affect the dark current of the overlying photodiodes. Managing this heat requires dedicated thermal vias and packaging designs that draw heat away from the pixel array. The temperature difference between the layers must be minimized to maintain image quality.
