Mechanical Cause
Geometric distortions occur when a thin semiconductor wafer or chip bows or twists away from a flat plane. In advanced packaging, die warpage complicates the alignment and bonding of components during high density assembly. These deviations are typically measured in microns across the diagonal of the chip.
The magnitude of the effect changes as the temperature fluctuates during the manufacturing process.
Stress Interaction
Internal stresses arise from the mismatch in the coefficients of thermal expansion between the silicon and the surrounding materials. While the silicon itself is rigid, die warpage becomes measurable when thin dies are attached to organic substrates or encapsulated in epoxy. The curing of molding compounds involves chemical shrinkage that pulls on the die edges.
Shadow moire or digital image correlation techniques are used to map these surface changes across the full operating range.
Interconnect Impact
Reliable electrical connections depend on maintaining a flat surface for the formation of solder bumps or wire bonds. If die warpage is excessive, the solder balls in a ball grid array may not touch the corresponding pads on the circuit board, leading to open circuits. During the reflow process, the chip may move, causing bridged connections where two solder joints melt into one.
Engineers design the stackup of the package to minimize these forces. Balancing the layers on both sides of the substrate often helps keep the assembly flat.
Measurement Standard
Metrology tools quantify the profile of the chip at room temperature and at the peak reflow temperature. A pass or fail grade for die warpage is determined by the specific requirements of the bonding equipment.
