Silicon Revision Impact on Open Drain Clock Stretching Dynamics
Silicon revisions alter open-drain driver impedance and state timing, turning compliant clock stretching into bus-halting race conditions across fast edges.
Repeated Start
Protocol Execution
Multi-device serial communications require transaction efficiency without losing control of the shared physical lines. A repeated start event occurs on an I2C bus when a master device issues a start condition without first sending a stop condition. This action allows the master to change transmission direction or address a different register without releasing the bus.
By skipping the stop phase, the master avoids the latency of re-initiating communication from an idle state.
Bus Ownership
Preventing other masters on a multi-master bus from grabbing control between transactions requires a continuous active state. Executing a repeated start maintains the master’s ownership of the bus throughout the entire multi-part message. This continuous hold prevents multi-master collision during complex transactions.
The bus remains busy, ensuring that other connected devices do not attempt to start their own transmissions during the read-write transition.
Master Control
Switching from a write operation to a read operation within a single transaction requires a seamless state change. To read from a specific register, the master first writes the register address and then issues a repeated start to initiate the read phase. This prevents another device from executing an operation on the slave in the middle of the register query.
The slave device maintains its internal state because the communication has not been terminated.
Signal Waveform
Transitioning the data line while the clock line remains high is the physical mechanism that signals the beginning of a new transaction block. In an I2C repeated start condition, the master pulls the serial data line low while the serial clock line is held high, mimicking a normal start sequence without a prior stop. This specific signal sequence must be timed accurately to avoid violating data hold and setup margins.
Oscilloscope measurements confirm that the signal timing conforms to protocol standards to avoid receiver confusion. Ensuring this transition is clean is a necessary step during hardware design verification. If the clock line falls too early, the slave devices may interpret the action as a clock pulse instead of a new start, causing communication to fail.