Silicon Die Revision Register Identification Verification Procedures
Verify silicon die revision registers via JTAG or serial readback before firmware boot to catch unannounced stepping changes and protect assembly yield.
Metal Layer Spin
Interconnect Revision
Modifications to the wiring layers of an integrated circuit allow engineers to fix logic errors or change the routing of signals without altering the base transistors. A metal layer spin involves creating new masks for the top levels of the semiconductor stack while keeping the bottom layers identical to the previous version. This approach is a cost effective way to iterate a design.
Logic Modification
Functional changes are achieved by rerouting the connections between existing logic gates that were already present in the base layers. If a metal layer spin is planned in advance, the designer will include spare gates in the layout to provide the flexibility needed for future fixes. This technique allows for the correction of timing issues or the addition of small features late in the development cycle.
Fabrication Efficiency
Using existing wafers that have already completed the base processing steps significantly reduces the time required to see the results of the change. A metal layer spin can be completed in a few weeks because only the final lithography and etching steps are required. This speed is essential for meeting tight market windows.
Mask Cost
Savings are realized because the most expensive masks are the ones used for the fine features at the bottom of the stack. By only changing the metal layers, the manufacturer avoids the high cost of a full mask set.