Automated Inspection Protocols for Detecting Silent Silicon Stepping Changes in SMT Packages
Automated boundary scan extraction combined with transmissive X-ray die metrology catches silent silicon stepping changes before SMT placement lines fault.
IDDQ Testing
Quiescent Characterization
Measurement of the steady-state supply current in a CMOS integrated circuit identifies manufacturing defects that functional testing overlooks. Engineers use iddq testing to detect gate oxide shorts and bridge faults that do not initially prevent the device from working. The process measures the current drawn while the clock is stopped and the circuit sits in a stable state.
Defect Detection
Physical anomalies like parasitic transistors or thin-film bridges cause an increase in the leakage current. Because an ideal CMOS circuit draws almost no current in a static state, iddq testing highlights any path that leaks charge. These defects often lead to reliability failures in the field even if the chip passes its initial speed tests.
Current Threshold
Establishing a pass-fail limit requires characterizing the intrinsic leakage of a healthy wafer. This baseline depends on the process node and the total number of transistors on the die. As transistor counts grow, the background noise rises and iddq testing requires delta iddq techniques to distinguish a defect from normal sub-threshold leakage.
Production Constraint
High-volume manufacturing lines must balance the thoroughness of the screen against the total test time required for iddq testing. The time required for the supply current to settle limits the speed of the test.