Sampling Architecture
Analog to digital converters operating with continuous time loop filters digitize signals without prior sample and hold circuitry. In a continuous time delta sigma adc, continuous time integration replaces discrete switched capacitor filtering before quantization. Continuous signal processing eliminates input switching transients that disturb driving amplifiers.
The architectural configuration places the sampling operation after the loop filter rather than at the analog input interface. As a result, high input impedance is maintained across wide frequency bands without requiring power hungry buffer amplifiers. Quantization noise shifts into higher spectral regions where digital decimation filters remove out of band energy.
Filter Integration
Inherent filtering action within the modulator loop attenuates high frequency interference before sampling occurs at the internal quantizer. A continuous time delta sigma adc integrates active RC loop filters into its feedback topology to shape in-band noise. Factory test procedures verify attenuation profiles against specified interferers.
Jitter Sensitivity
Phase noise on the sampling clock directly degrades signal to noise ratios in continuous time architectures. Clock timing variations alter feedback pulse areas inside a continuous time delta sigma adc, converting phase jitter into voltage noise. External clock sources must maintain phase jitter below specified thresholds.
Verification Limit
Metrological qualification establishes dynamic range limits across operational temperature bands. Thermal variations shift filter pole locations in a continuous time delta sigma adc, altering overall loop stability. Automated test equipment verifies target performance boundaries before device release.