Calculating Group Delay in Delta Sigma Converters

Decimation

Delta-sigma architectures translate high-speed single-bit or multi-bit modulator bitstreams into high-resolution PCM output codes. Conversion accuracy depends on oversampling the input signal far above the Nyquist rate, shaping quantization noise into high frequencies, and filtering that noise out of the band of interest. The digital decimation filter executes this noise removal while downsampling the high-rate bitstream to the target output data rate.

Group delay in this signal chain represents the time delay experienced by the envelope of various sinusoidal frequency components through the converter.

Modulator Oversampling and Digital Filtering

Primary signal conversion relies on delta-sigma modulators operating at sampling rates significantly above the Nyquist frequency. The ratio between the modulator clock frequency and the output data rate defines the oversampling ratio. Quantization noise distribution across the frequency spectrum remains uniform in a un-shaped system, but a delta-sigma modulator forces noise out of the signal band into higher frequencies.

Modulators achieve this by placing feedback loops around the quantizer, creating a high-pass noise transfer function.

Modulators oversample signal inputs.

Downsampling requires filtering to eliminate out-of-band noise before reducing the sampling rate. Without pre-filtering, high-frequency quantization noise aliases down into the baseband, degrading signal-to-noise ratio. The digital decimation filter accomplishes both suppression of quantization noise and reduction of sample rate.

Because the decimation filter operates directly on the raw modulator clock, its structure dominates the temporal behavior and phase response of the entire conversion subsystem.

Mathematical Roots of Cascaded Delay

Calculating total phase shift across a digital signal chain requires summing the contributions of individual functional blocks. Group delay, denoted as tau, is defined mathematically as the negative derivative of the filter phase response with respect to angular frequency:

Group Delay Equation ~ tau(omega) = -d(theta(omega)) / d(omega)

When the filter exhibits linear phase, the derivative remains constant across all baseband frequencies. Linear phase guarantees that all spectral components pass through the converter with identical time delay, preserving complex waveform shapes without phase dispersion. Finite impulse response structures with symmetric or antisymmetric impulse response coefficients naturally produce constant group delay.

A fifth-order sinc filter downsampling by a factor of 64 at a 10.24 MHz modulator clock yields a group delay of 15.625 microseconds.

Cascaded integrator-comb architectures, commonly designated as sinc filters, serve as the primary decimation stage in most delta-sigma converters. A sinc filter contains K identical stages of integrators running at the modulator clock rate, followed by K comb stages running at the downsampled rate. The z-domain transfer function of a K-th order sinc filter with decimation factor M equals:

Sinc Transfer Function ~ H(z) = ((1 – z^(-M)) / (M (1 – z^(-1))))^K

Evaluating the phase response of this transfer function yields an exact equation for sinc filter group delay. Because a sinc filter represents an FIR structure with M K – K + 1 taps, its group delay expressed in seconds is strictly constant across all frequencies:

Sinc Group Delay ~ tau_sinc = (K (M – 1)) / (2 f_mod)

Where f_mod is the modulator sampling frequency in hertz, K represents the filter order, and M defines the decimation factor. Expressing group delay relative to the final output sample period, t_s = M / f_mod, illustrates that sinc delay scales directly with filter order K.

Sinc Delay in Output Samples ~ tau_sinc_samples = (K (M – 1)) / (2 M) approximately equals K / 2

Higher sinc filter orders deliver steeper attenuation of modulator quantization noise, but proportionally extend the signal delay through the decimation pipeline.

Vendor literature frequently characterizes digital filter delay as zero-phase latency by citing only the group delay of the passband midpoint while omitting the processing delay of internal accumulator resets.

Tap

Linear phase finite impulse response networks enforce equal delay across all passband spectral components. The physical tap length of an FIR filter determines both its stopband attenuation capability and its signal latency. In multi-stage decimation structures, high-order initial sinc stages reduce the data rate down to an intermediate frequency, allowing subsequent FIR stages to operate with fewer taps to achieve sharp transition bands.

Calculating Multi-Stage FIR Chain Latency

Determining end-to-end converter delay involves tracking sampling rate transitions across consecutive decimation steps. Total latency equals the direct sum of group delays contributed by each individual processing stage expressed in seconds. Calculating delay in output sample clocks requires converting each stage delay to seconds before normalizing to the final output sample period.

Filter taps dictate delay.

A typical high-resolution industrial delta-sigma converter utilizes a three-stage decimation topology. Stage 1 consists of a Sinc4 filter reducing sample rate by decimation factor M1. Stage 2 employs a half-band linear-phase FIR filter with N2 taps downsampling by two.

Stage 3 employs a wideband droop-compensation FIR filter with N3 taps downsampling by two to flatten the passband response attenuated by the primary sinc filter.

Summing these delays requires establishing the operational sampling clock at the input of each stage:

Input Rate Stage 1 ~ f_in1 = f_mod

Input Rate Stage 2 ~ f_in2 = f_mod / M1

Input Rate Stage 3 ~ f_in3 = f_mod / (2 M1)

Final Output Rate ~ f_s = f_mod / (4 M1)

Evaluating group delay across all three stages yields:

Stage 1 Delay ~ tau_1 = 2 (M1 – 1) / f_mod

Stage 2 Delay ~ tau_2 = (N2 – 1) / (2 f_in2) = (N2 – 1) M1 / (2 f_mod)

Stage 3 Delay ~ tau_3 = (N3 – 1) / (2 f_in3) = (N3 – 1) M1 / f_mod

Total Signal Chain Group Delay ~ tau_total = tau_1 + tau_2 + tau_3

Worked Derivation of Stage Delay Summation

An industrial control system employs a 24-bit delta-sigma converter clocked at 6.144 MHz to evaluate total signal processing latency. The converter configuration uses a Sinc4 filter with M1 = 32, followed by a 31-tap half-band FIR stage decimation by 2, and a 63-tap compensation FIR stage decimation by 2.

The calculation sequence follows precise mathematical steps:

1. Calculate the modulator clock period: t_mod = 1 / 6,144,000 = 162.76 nanoseconds.
2. Calculate Stage 1 (Sinc4, M1 = 32) group delay: tau_1 = (4 (32 – 1)) / (2 6,144,000) = 124 / 12,288,000 = 10.091 microseconds.
3. Calculate Stage 1 output sampling rate: f_in2 = 6,144,000 / 32 = 192 kHz.
4. Calculate Stage 2 (31-tap FIR) group delay: tau_2 = (31 – 1) / (2 192,000) = 30 / 384,000 = 78.125 microseconds.
5. Calculate Stage 2 output sampling rate: f_in3 = 192,000 / 2 = 96 kHz.
6. Calculate Stage 3 (63-tap FIR) group delay: tau_3 = (63 – 1) / (2 96,000) = 62 / 192,000 = 322.917 microseconds.
7. Calculate final converter output sampling rate: f_s = 96,000 / 2 = 48 kHz (output period t_s = 20.833 microseconds).
8. Sum absolute stage delays: tau_total = 10.091 + 78.125 + 322.917 = 411.133 microseconds.
9. Normalize total delay to final output sample periods: tau_samples = 411.133 / 20.833 = 19.734 sample periods.

Clocks drive converter timing.

This explicit derivation demonstrates that the final compensation stage contributes over 78 percent of total converter latency. High tap counts at lower sample rates create substantial time lags, even though the primary sinc filter downsamples the bulk of the high-frequency spectrum.

Symmetrical impulse responses preserve phase alignment across complex sensor signals at the expense of fixed pipeline latency.

Phase

Group delay represents the negative rate of change of filter angular response with respect to frequency. Linear phase filters keep group delay flat across the entire passband, ensuring that multi-tone or transient input signals pass through the converter without temporal phase distortion. Non-linear phase decimation filters trade flat group delay for reduced passband latency, shifting coefficients to accelerate step-response settling times.

How Do Non Linear Phase Decimators Reduce Latency?

Asymmetrical impulse responses concentrate filter energy near early coefficient indices rather than centering it symmetrically. Minimum-phase FIR filters and Infinite Impulse Response (IIR) digital decimation topologies utilize this property to minimize phase delay for low-frequency signal components.

Minimum phase reduces lag.

By moving zeros inside the unit circle of the z-plane, a minimum-phase filter yields the smallest possible group delay for a given magnitude response specification. Passband latency drops significantly compared to an equivalent-length linear-phase FIR filter. The group delay of a minimum-phase decimation filter is non-constant, exhibiting maximum latency at low frequencies and declining toward higher frequencies near the passband edge.

IIR decimation filters, such as Butterworth or Elliptic topologies, deliver steep stopband rejection with very low tap counts. However, their poles generate frequency-dependent group delay dispersion. High-frequency signal components near the cutoff frequency experience greater latency than low-frequency components.

Dispersion introduces phase distortion, altering signal peak shapes in precision dynamic measurements.

Minimum-phase digital filters trade linear dispersion across frequency channels for immediate step response arrival.

Group Delay Variation across Passband Boundaries

In non-linear phase decimation networks, group delay varies as a function of signal frequency. Quantifying group delay distortion across the usable bandwidth requires evaluating the maximum group delay deviation, delta tau_g, across the baseband spectrum.

Group Delay Variation ~ delta tau_g = max(tau_g(f)) – min(tau_g(f)) for f in

Passband group delay variation causes different spectral components of a transient event to arrive at the output register at different times. In acoustic, vibration, or multi-axis strain measurements, phase dispersion distorts time-domain pulse shapes and introduces phase errors during inter-channel cross-correlation analysis.

Phase response stays linear.

Linear phase architectures eliminate group delay variation entirely. The trade-off remains fixed latency against phase integrity. Wideband audio and seismic sensors select linear phase FIR chains to preserve signal wave shapes.

Motion control feedback loops and multiplexed data acquisition systems select fast-settling IIR or minimum-phase filters to maximize control bandwidth and eliminate pipeline delay.

Miscalculating filter latency in multi-axis sensor fusion systems shifts control loop stability margins into uncompensated phase lags.

Bench

Empirical extraction of converter latency demands precise cross-correlation between physical analog inputs and digital frame header timestamps. Bench measurement techniques isolate the converter group delay from continuous-time signal conditioning, test instrumentation delays, and interface buffer latency.

Phase Derivative Extraction via FFT Analysis

Spectral phase evaluation converts time-domain step or impulse responses into frequency-domain phase curves. Driving the analog front-end with a band-limited impulse or swept sine wave allows direct capture of digital output frames. Computing the Fast Fourier Transform of the captured time series yields the complex frequency response, H(f).

Extracting the unwrapped phase function, theta(f), precedes digital differentiation:

Empirical Group Delay ~ tau_measured(f) = -1 / (2 pi) (delta theta(f) / delta f)

Noise in measured phase data introduces severe variance during numerical differentiation. Applying polynomial smoothing filters or performing linear phase regressions across the passband stabilizes empirical delay calculations. Bench tests must record data over multiple frames to average out sampling phase ambiguity relative to the asynchronous input signal trigger.

Analog Anti Aliasing Filter Phase Shift

Upstream continuous-time low-pass networks contribute phase slope prior to the analog-to-digital converter input terminals. A single-pole continuous-time RC filter placed before the modulator introduces frequency-dependent group delay:

RC Filter Group Delay ~ tau_rc(f) = R C / (1 + (2 pi f R C)^2)

At low frequencies (f much less than 1 / (2 pi R C)), the analog filter adds a baseline delay equal to its time constant, tau = R C. Second-order active anti-aliasing drivers introduce additional phase lag near their corner frequencies. Total signal path delay combines continuous-time analog group delay with discrete-time digital decimation delay.

Latency shifts timing.

Bench validation error sources must be identified and accounted for during empirical signal chain latency audits.

• Clock Jitter Artifacts ~ Phase noise on the master modulator clock shifts downsampling sample boundaries, introducing random phase variance across sequential FFT acquisition windows.
• Trigger Offset Uncertainty ~ Asynchrony between the analog pulse generator clock and the converter conversion start signal creates a fixed sub-sample timing ambiguity up to one modulator clock period.
• Input Settling Delays ~ Finite op-amp output impedance coupled with modulator switched-capacitor input loading creates subtle continuous-time settling lags that appear as baseline phase shifts.
• FFT Windowing Distortion ~ Spectral leakage from improper window selection distorts the unwrapped phase slope near passband edge boundaries, corrupting numerical derivative estimates.

Compliance with ISO 26262 functional safety mandates timing verification across both the analog front-end and digital decimation chain to guarantee deterministic latency under sensor fault conditions.

Whether internal digital filter reset mechanisms can dynamically alter group delay during real-time sample rate changes without corrupting adjacent data frames remains an active area of converter design.

Spec

Component datasheets quote timing characteristics using inconsistent reference points across manufacturers. Selecting delta-sigma converters for latency-sensitive feedback systems requires translating vendor terminology into strict temporal definitions.

Datasheet Terminology and Discrepancies

Manufacturer documentation often fails to define whether published delay figures measure from analog input transition to digital output valid signal. Common terms found in converter datasheets include group delay, pipeline latency, filter delay, and settling time.

Delay remains constant.

Group delay strictly specifies the phase derivative slope across the passband. Pipeline delay reflects the total digital clock cycles required for a single conversion sample to propagate from the modulator input through all decimation stages to the SPI or I2C output interface register. Settling time measures the time elapsed from a step input change until the output code settles within a specified percentage (such as 0.001 percent) of full-scale value.

For a linear-phase FIR decimation filter, full step-response settling requires twice the filter group delay. Equating group delay with complete step response settling leads to catastrophic timing errors in multiplexed data acquisition systems.

System Budget Allocation for High-Speed Control

Closed-loop feedback loops require deterministic latency allocations across sensor acquisition, conversion, and communication interfaces. Industrial servo drives, active noise cancellation systems, and grid-tied power electronics operate under strict total loop delay budgets.

Decimation reduces sample rates.

When selecting a delta-sigma converter for fast control loops, digital decimation settings must balance noise suppression against phase margin consumption. High decimation ratios improve effective number of bits but introduce excessive phase delay that degrades control loop stability margins.

• Selectable Decimation Modes ~ Flexible decimation engines permit dynamic switching between linear phase Sinc architectures for precision static measurements and low-latency fast-settling modes for fast transient responses.
• Hardware Sync Pin Response ~ Dedicated pin-driven filter reset capabilities allow external microcontrollers to synchronize internal decimation accumulators to absolute control cycle clocks.
• Group Delay Linearity ~ Flat phase response guarantees zero phase distortion across the control bandwidth, eliminating phase compensation requirements in feedback control algorithms.
• Passband Ripple Trade Off ~ Sharp transition bands requiring higher FIR tap counts increase group delay, while wider transition bands shorten filter latency at the expense of potential aliasing.

Programmable logic controllers operating on sub-millisecond loop times require converters with group delays strictly bounded below five output clock cycles.

Adopting IEEE 1451.4 smart transducer interface requirements enforces published latency parameters to include all digital decimation steps, changing procurement verification from raw modulator clock rates to end-to-end sample delivery times.