Mitigating Switched Capacitor ADC Load Transient Drift in Integrated References
Mitigating switched-capacitor reference droop requires a low-ESR reservoir capacitor sized to charge-redistribution ratios and Kelvin-connected to analog ground.
Charge Redistribution
Physical Mechanism
An electrostatic process in mixed-signal circuits balances voltage levels across a capacitive network by sharing electrical charge. During this operation, charge redistribution occurs when switches connect separate capacitors, causing them to equalise their potentials. The total charge remains constant while the node voltages settle to a new equilibrium value.
This settling is bounded by the series resistance of the switches.
Circuit Operation
A successive approximation register uses this charge allocation to resolve analog signals. Switches route the input voltage to a set of binary-weighted capacitors, and then the circuit alters the connections to execute charge redistribution sequentially. In each cycle, the digital logic compares the resulting voltage against a threshold to determine one bit.
This action requires precise timing to ensure the voltages settle before the comparator makes its decision. Fast clock rates can disrupt this process if the time allowed is shorter than the RC time constant of the network.
Performance Limitation
Unwanted switch resistance and parasitic capacitances introduce errors into the final voltage. When charge redistribution takes place, these parasitic elements steal a fraction of the charge, leading to non-linear steps. Thermal noise also limits the precision of the charge transfer.
Designers must choose capacitor values that are large enough to dominate these parasitic effects.
Calibration Method
Systematic mismatch is corrected by adjusting the effective weight of each capacitor. Internal digital calibration arrays add or subtract small capacitive units to restore linearity. This adjustment removes the offset error.
It ensures the conversion remains accurate under varying conditions.