Mitigating Switched Capacitor ADC Load Transient Drift in Integrated References
Mitigating switched-capacitor reference droop requires a low-ESR reservoir capacitor sized to charge-redistribution ratios and Kelvin-connected to analog ground.
SAR ADC Bit Cycling
Operational Phase
A sequential decision-making algorithm executed by internal logic gates resolves an analog voltage into a digital code. During this process, SAR ADC bit cycling sequentially tests each bit from the most significant to the least significant. Each step compares the unknown analog voltage against the output of an internal DAC.
This action requires a stable voltage reference to ensure each decision is accurate.
Search Mechanism
Binary search algorithms narrow down the voltage range by half with each clock cycle. The SAR ADC bit cycling begins by setting the most significant bit to one and comparing the resulting voltage. If the input is higher, the bit remains one, otherwise it is set to zero.
This process repeats for every subsequent bit until the full resolution is achieved.
Timing Constraint
Each bit trial must allow enough time for the DAC voltage and the internal comparator to fully settle. High clock frequencies reduce the available time for each cycle. This can lead to decision errors if the voltages have not stabilized.
Designers must balance conversion speed with settling accuracy.
Calibration Technique
Digital correction algorithms correct errors caused by dynamic settling issues or capacitor mismatch. This adjustment ensures high-resolution performance.