Deep Trench Isolation Performance in near Infrared Global Shutter Pixels

Path

Silicon turns transparent beyond visible thresholds. Incoming radiation at 850 nm and 940 nm encounters an indirect electronic bandgap of 1.12 eV at room temperature, which lowers the optical absorption coefficient to roughly 600 cm⁻¹ at 850 nm and barely 100 cm⁻¹ at 940 nm. Photons travel tens of micrometers unabsorbed.

Achieving acceptable quantum efficiency at these wavelengths forces image sensor architectures to increase the active substrate absorption thickness from the standard 3 µm visible baseline up to 8 µm, 12 µm, or even 15 µm.

Attenuation Limits in Substrate Volumes

Photons at near-infrared wavelengths penetrate through thin epitaxial strata without generating charge carriers inside target depletion regions. When an unthinned or insufficiently thickened substrate absorbs 940 nm illumination, the peak generation profile stretches tens of micrometers beneath the collecting cathode. Backside-illuminated image sensors capture this spectrum only when incoming rays travel through an elongated optical trajectory.

Surface texturing, such as inverted pyramid arrays etched into the silicon backside, scatters incoming normal-incidence rays into oblique angles. Diffraction gratings integrated onto the entry interface achieve equivalent trajectory redirection, prolonging the internal transit. When light bounces internally between the back surface and the front dielectric metallization, the effective absorption distance multiplies.

This optical gain introduces an acute penalty: slanted rays propagate sideways across several pixel pitches before generating an electron-hole pair.

Optical absorption at 940 nm requires a 40 µm path length in bulk silicon to capture 63 percent of incident photons at 25°C.

Carrier Dispersion across Depletion Boundaries

Photoelectrons generated outside depletion regions wander randomly until recombining or entering an adjacent potential well. In standard visible pixels with thin active silicon, vertical drift fields quickly sweep carriers into the photodiode. Thickened silicon layers necessary for near-infrared sensitivity leave deep, quasi-neutral field-free zones where diffusive transit dominates over drift.

Carrier diffusion destroys spatial modulation transfer. An electron created 10 µm below the collecting junction displays an isotropic spatial probability cloud, drifting laterally into neighboring pixels with equal likelihood. At typical 2.2 µm or 3.0 µm pixel pitches, this dispersion induces severe electrical crosstalk, eroding the modulation transfer function above Nyquist spatial frequencies.

Omitting vertical barriers forces system architects to double illumination power or accept uncorrectable point-spread blurring across high-speed tracking frames.

Wall

Dielectric barriers etched vertically between pixels counteract lateral carrier diffusion and optical spillover. Trench isolation structures, known as DTI, carve physical boundaries into the silicon matrix to segment individual active areas. Replacing conductive bulk silicon with low-refractive-index materials turns pixel interfaces into reflective optical guides while establishing electrostatic isolation.

Dielectric Interfaces and Total Reflection

Silicon exhibits a refractive index of approximately 3.6 in the near-infrared spectrum. Filling an isolation trench with silicon dioxide, which holds an index of 1.46, establishes an optical boundary governed by Snell’s law. Light striking the trench interface from within the silicon at angles greater than roughly 24 degrees from the normal undergoes total internal reflection.

Scattered rays remain confined within the source pixel column rather than bleeding into neighbors.

Refractive boundaries alter photon trajectories. Beyond pure silicon dioxide, multi-layer trench liners incorporating higher-permittivity dielectrics like silicon nitride or aluminum oxide combined with polysilicon or low-index air voids fine-tune optical containment. Air-gap trench schemes push the critical reflection angle down to 16 degrees, trapping high-angle scattered photons.

Void stability, however, introduces mechanical vulnerability during thermal cycling and metallization anneals.

Is Full Depth Isolation Manufacturable in High Aspect Ratios?

Fabricating isolation barriers through 8 µm to 15 µm of active silicon requires deep reactive ion etching with aspect ratios exceeding 30:1. The Bosch process, which alternates sulfur hexafluoride etching with octafluorocyclobutane polymer deposition, yields vertical sidewall profiles across substantial depths. Etch profiles degrade with depth.

Scalloping along the trench walls causes optical scatter, while trench narrowing or bow distortion compromises isolation uniformity from die center to edge.

Partial-depth backside trench isolation (BDTI) etches downward from the illuminated rear surface but stops short of frontside electronic circuitry. Frontside trench isolation (FDTI) etches from the circuit surface down into the substrate before wafer thinning. Full-depth trench isolation completely isolates adjacent pixels throughout the entire silicon layer.

Combining backside etching with frontside etching requires sub-micron alignment accuracy across bonded wafer pairs, as misaligned interfaces generate dislocations that poison carrier lifetimes.

Narrower trenches preserve capacitive fill factors but heighten the risk of void formation during oxide deposition.

Shield

Global shutter image capture requires temporary in-pixel charge storage while the active array reads out line by line. Rolling shutter sensors integrate and transfer charge sequentially, whereas global shutter devices expose all pixels simultaneously, shifting captured photoelectrons into shielded memory nodes. Near-infrared photons, possessing long attenuation lengths, breach traditional surface metallization barriers, generating stray charge inside these intermediate storage sites.

Parasitic Light Sensitivity in High-Speed Readout

Parasitic light sensitivity measures the susceptibility of an unshielded memory node to unwanted illumination during the readout cycle. The figure is expressed as the reciprocal ratio of memory node sensitivity to photodiode sensitivity, with high-performance architectures demanding values lower than -80 dB, corresponding to one part in ten thousand. When intense illumination strikes an image sensor during rolling readout of stored frames, leakage into the storage element causes severe vertical smear and dynamic range suppression.

Tungsten shields block overhead illumination. Standard process nodes deposit opaque tungsten or aluminum light shields directly over the storage diode or floating diffusion node. Front-incident visible rays cannot penetrate these planar metal barriers.

Long-wavelength photons, conversely, reflect from backside texturing, diffuse laterally under the edges of tungsten plates, and generate electron-hole pairs directly inside the shielded potential well.

Parasitic light sensitivity degrades from -85 dB at 550 nm to worse than -62 dB at 940 nm when lateral isolation trenches terminate early.

Will Capacitive Storage Nodes Prevent Optical Bleed?

Charge-domain global shutter pixels rely on pinned storage diodes or shielded charge-transfer gates situated adjacent to the pinned photodiode. Voltage-domain pixels transfer charge immediately to a floating diffusion node or an analog metal-insulator-metal storage capacitor. In both architectures, proximity between the sensing photodiode and the storage node invites optical and electrical cross-coupling.

Physical barriers isolate the sensitive storage capacitor from the primary light-collecting region. Surrounding the storage diode with full-perimeter DTI boundaries prevents laterally diffusing carriers from crossing into the memory node. Dielectric trench walls divert oblique photon trajectories upward toward front metallization or downward toward the substrate, starving the storage well of scattered near-infrared illumination.

A structured evaluation of parasitic light sensitivity across device configurations isolates several decisive mechanisms:

• Optical diffraction suppression occurs when trench barriers prevent lateral propagation of glancing-angle waves beneath tungsten aperture shields.
• Diffusive carrier interception prevents bulk-generated photoelectrons from wandering across p-n junction isolation boundaries into unprotected storage nodes.
• Capacitive coupling attenuation limits parasitic cross-talk voltages between adjacent transfer gate lines during high-frequency readout sequences.
• Storage capacity preservation maintains full-well capacity by confining electrostatic fields within the designated memory storage volume.

Shutter efficiency drops during long readouts. When integrating low-light near-infrared scenes under pulsed laser or LED illumination, the sensor holds integrated charges inside the memory node for hundreds of microseconds while bright ambient light continues illuminating the array. Insufficient isolation depths allow background solar radiation to corrupt the stored signal, degrading high-speed structured-light depth maps.

Foundries routinely attribute degraded shutter ratios to oblique package reflection rather than admitting micro-trench termination shortfalls.

Dark

Etching deep, narrow vertical chasms into monocrystalline silicon creates immense surface area exposed to lattice disruption. Every square centimeter of trench wall introduces uncoordinated chemical bonds, broken crystal symmetry, and atomic displacement. These surface defects act as generation-recombination centers within the silicon bandgap, drastically escalating dark current generation and creating fixed-pattern noise across pixel arrays.

Mid-Gap Traps and Shockley-Read-Hall Kinetics

Silicon lattice terminations along etched sidewalls present unbonded valence orbitals termed dangling bonds. According to Shockley-Read-Hall theory, localized electronic energy levels near the center of the bandgap maximize thermal generation rates of electron-hole pairs. In the presence of strong electric fields near depletion regions, trap-assisted tunneling further amplifies carrier production.

Dangling bonds create generation centers. Thermally generated electrons drift directly into neighboring collection wells, masquerading as true optical signals. In global shutter pixels, dark current generated along trench walls near the storage node progressively fills the potential well during readout, creating position-dependent offset shading across the sensor matrix.

Thermal excitation accelerates dark carrier production. Operating at elevated ambient temperatures, such as automotive environments at 85°C to 105°C, doubles dark current density roughly every 6°C to 8°C. Without robust surface passivation, high-aspect-ratio trench arrays produce unacceptable dark signal non-uniformity and an extensive population of white spot pixels.

Field-Effect Passivation Mechanics

Suppressing thermal generation requires neutralizing mid-gap states through chemical passivation and bending local electronic bands through field-effect passivation. Chemical passivation saturates broken bonds with hydrogen, forming covalent silicon-hydrogen pairs that push defect states out of the active bandgap. Hydrogen bonds dissociate under sustained high-temperature processing, necessitating supplementary electrostatic protection.

Fixed negative charge repels electrons. Depositing thin dielectric films of aluminum oxide via atomic layer deposition introduces an innate negative fixed charge density exceeding 10¹² cm⁻². This negative field creates an accumulation layer of holes along the p-type trench perimeter while repelling minority electrons away from interfacial trap sites.

Starving the surface of electrons suppresses the Shockley-Read-Hall generation rate by several orders of magnitude.

Atomic layer deposition of aluminum oxide at 250°C achieves interface state densities below 1.5 × 10¹⁰ eV⁻¹ cm⁻² along 30:1 trench profiles.

Implementing effective passivation faces tight thermal constraints in modern stacked-wafer manufacturing. A sequential implementation path balances mechanical and thermal parameters:

1. Deep reactive ion etching forms pixel-isolation chasms with controlled sidewall taper angles between 88.5 and 89.5 degrees.
2. Sacrificial thermal oxidation strips subsurface crystal damage caused by high-energy ion bombardment during etching.
3. Atomic layer deposition coats trench walls with an amorphous aluminum oxide film exhibiting uniform step coverage.
4. Low-temperature inert gas annealing activates field-effect passivation without exceeding the 400°C thermal limit of copper bonding pads.
5. High-density chemical vapor deposition fills remaining trench voids with silicon dioxide or polysilicon cores to restore mechanical rigidity.

Whether atomic layer passivation can maintain uniform negative fixed charge across thirty-to-one aspect ratio trenches without introducing localized structural strain remains unresolved across high-volume production lots.

Foundry

Manufacturing deep trench structures within sub-3 µm pixel architectures challenges commercial wafer fabrication infrastructure. While visible-light rolling shutter sensors rely on mature single-wafer processing, near-infrared global shutter sensors depend on 300 mm back-illuminated wafer stacking platforms. Adding multi-micron vertical trenches introduces mechanical warpage, pattern distortion, and yield degradation that directly inflate bill-of-materials costs.

Lithographic Alignment across Bonded Stacks

Modern back-illuminated image sensors bond an active pixel wafer directly to an underlying application-specific integrated circuit wafer using direct oxide-oxide or hybrid copper-copper fusion bonding. Etching trenches from the illuminated back surface requires lithographic steppers to align trench patterns to circuit layers buried beneath several micrometers of opaque silicon. Infrared alignment optics resolve frontside fiducial markers through the substrate, maintaining alignment tolerance within 50 nanometers.

Wafer warpage ruins lithographic overlay. High-aspect-ratio trenches etched across millions of pixel repetitions induce substantial internal stress. When filled with dielectrics exhibiting thermal expansion coefficients different from bulk silicon, wafers bow into concave or convex profiles.

Bowing exceeding 40 µm leads to chuck clamping failures, depth-of-focus defocusing, and overlay drift across stepper exposure fields.

Tool Availability and Sourcing Volatility

Carving aspect-ratio trenches requires specialized cryogenic or advanced pulsed-gas deep reactive ion etching equipment. Atomic layer deposition tools capable of coating narrow chasm sidewalls with atomic monolayer uniformity across 300 mm diameters represent substantial capital expenditure. Tool availability dictates delivery schedules.

Foundries lacking dedicated batch-ALD clusters experience significant cycle time extensions when shifting from visible image sensor production to specialized near-infrared global shutter runs.

Dual-sourcing strategies face significant friction due to proprietary trench process integration. A design qualified on a foundry platform utilizing frontside oxide-filled trenches cannot transfer to an alternate foundry employing backside partial trenches without redesigning the pixel layout, optical stack, and storage node shielding geometry. Sourcing teams must audit wafer acceptance test data to monitor trench depth uniformity, sidewall roughness, and interface trap densities.

Standard SEMI M1 specifications mandate wafer bow limits below thirty micrometers, because exceeding that threshold invalidates steppers’ depth-of-focus compensation across dual-sided trench alignment layers.