Lattice Deformation
Internal lattice forces in semiconductor wafers result from thermal mismatches between the bulk material and deposited thin films or external packaging. Silicon substrate strain describes the physical distortion of the atomic grid that occurs when these forces exceed the natural equilibrium. This deformation can be intentionally induced to improve electron speed or unintentionally created during assembly.
It alters the electrical properties of the transistors and can lead to structural failure if left unmanaged.
Carrier Mobility
Compressing or stretching the atomic lattice changes the path that electrons take through the semiconductor. Controlled silicon substrate strain is a common technique in modern chip manufacturing to enhance performance. By applying a tensile force, the resistance of the channel is reduced.
Curvature Measurement
Detection of the stress level is performed by measuring the bow of the wafer with a laser. As silicon substrate strain increases, the wafer warps into a concave or convex shape. This curvature is used to calculate the total force being applied by the surface layers.
Yield Impact
Excessive warping can prevent the wafer from being properly handled by automated tools. If silicon substrate strain is too high, the lithography process will fail to focus correctly. This results in a loss of transistors and a reduction in the number of working chips.
