Mitigating Switched Capacitor ADC Load Transient Drift in Integrated References
Mitigating switched-capacitor reference droop requires a low-ESR reservoir capacitor sized to charge-redistribution ratios and Kelvin-connected to analog ground.
Sampling Capacitor Array
Hardware Architecture
A structured network of discrete capacitive components on a silicon substrate stores the analog input voltage during the conversion phase. In a successive approximation analog-to-digital converter, a sampling capacitor array is implemented using binary-weighted values. This network connects to the comparator inputs and is switched sequentially during the decision phase.
It must be isolated from digital switching noise to prevent signal corruption.
Charge Distribution
During the sampling phase, the analog input is connected to all the capacitors in the network. This sampling capacitor array holds the sampled voltage on its bottom plates while the top plates are held at a fixed potential. Once the sampling switch opens, the charge is trapped.
The circuit then redistributes this charge by switching the bottom plates to the reference voltage.
Performance Matching
Mismatches between the individual capacitor elements introduce non-linearity errors in the conversion. Manufacturers use common-centroid layouts to minimize the effects of temperature and process gradients across the silicon die. Even small physical differences can alter the binary weights.
This mismatch limits the effective resolution of the converter.
Calibration Strategy
Integrated digital-to-analog sub-arrays adjust for mismatch by adding small correction charges. This digital correction removes the need for overly large capacitors, saving silicon area.