Internal Bandgap Voltage Error Reduction in High Gradient Layouts
Internal bandgap voltage errors in high gradient layouts are reduced by common-centroid matching, thermal isolation trenching, and package stress mitigation.
Piezo-Junction Effect
Stress Sensitivity
Physical changes in the bandgap energy of a semiconductor crystal under mechanical stress alter the current-voltage characteristics of pn junctions. The piezo-junction effect causes the forward-bias voltage of silicon diodes to shift, which is a major source of error in temperature sensors and bandgap reference circuits.
Reference Drift
When package stress is transferred to the silicon die, the saturation current of the junctions changes, altering the voltage output. This stress-induced variation can degrade the accuracy of high-precision measurement devices over time or after circuit board assembly. The magnitude of this shift depends heavily on the orientation of the diode relative to the silicon crystal lattice.
Mitigation Technique
Minimizing this effect involves both structural and layout changes. Resilient die attach materials absorb much of the mounting stress, while trenches cut into the silicon isolate the active regions from mechanical forces. Designers also place critical diodes in the center of the die where the stress gradients are lowest.
These layout constraints are verified using stress-simulation tools during the development phase. Furthermore, multi-diode array layouts are used to average out the stress vectors across the active area.
Measurement Method
The susceptibility of a design is evaluated by applying controlled mechanical loads to the package while monitoring the change in reference voltage. This characterization helps to define the maximum allowable assembly force and board-bending limits. The resulting data are used to set the calibration routines.