Internal Bandgap Voltage Error Reduction in High Gradient Layouts
Internal bandgap voltage errors in high gradient layouts are reduced by common-centroid matching, thermal isolation trenching, and package stress mitigation.
Register Trim
Digital Adjustment
Calibration methods for integrated circuits use digitally controlled switches to adjust the value of internal resistors or current sources. Implementing a register trim allows the output of an analog circuit to be fine-tuned after packaging, correcting for manufacturing variations without requiring physical modification of the silicon.
Tuning Architecture
Binary-weighted arrays of components connect to digital switches to enable this tuning. By loading specific code patterns into the control register, the active component values are modified to optimize performance. This digital adjustment enables high-precision tuning of reference voltages, gain stages and oscillator frequencies.
Memory Reliability
Nonvolatile memory registers store these calibration codes permanently on the chip. During boot-up, the system automatically loads these values into the active registers to configure the analog blocks. Ensuring the long-term retention of these stored bits is critical, as any memory corruption would cause the circuit to revert to an uncalibrated state.
Error-correcting codes and redundant bit cells are often integrated to prevent such failures.
Calibration Protocol
Automated test equipment executes the adjustment process during final production testing. By applying a known input and measuring the output, the tester calculates the optimum trim code and programs it into the memory. This process is completed in a few milliseconds per device.