Master Supply Agreement Drift Limits and Microelectronic Acceptance
Master supply agreements enforce microelectronic acceptance by establishing guard-banded drift boundaries that partition thermal, packaging, and aging errors.
Passivation Stress Relaxation
Material Phenomenon
Dielectric films used to protect semiconductor devices undergo structural changes that relieve the mechanical tension accumulated during deposition. The process of passivation stress relaxation involves the reorganization of the atomic structure of silicon nitride or silicon dioxide layers under thermal and mechanical loads. This reorganization can lead to the formation of physical voids in the underlying metal lines.
Semiconductor foundries monitor this behavior to prevent long-term reliability failures.
Physical Mechanism
High deposition temperatures and mismatched thermal expansion coefficients create massive residual stress in thin dielectric films. In the context of passivation stress relaxation, this stress is slowly released through plastic flow, driving metal migration in the aluminum or copper lines beneath. The metal is forced to fill or create gaps, forming voids that can eventually lead to open circuits.
Measuring the rate of this relaxation helps engineers optimize deposition parameters.
Reliability Consequence
Interconnect damage caused by atomic migration leads to increased line resistance and eventual electrical open circuits. Testing passivation stress relaxation involves thermal storage at elevated temperatures to accelerate the relaxation.
Optimization Method
Adjusting the chemical composition and deposition energy of the protective layer helps balance the intrinsic stress of the film. Process engineers select specific deposition recipes that minimize passivation stress relaxation by creating a low-stress dielectric structure. Testing these modifications requires wafer-level strain measurements before and after thermal baking.
This procedure ensures the long-term integrity of the metal interconnects in the field.