Standard Bandgap Reference Layout Rules for Isothermal Precision Circuits
Precision bandgap layout demands common-centroid transistor symmetry, localized thermal guard isolation, and PCB stress slots to achieve sub-5 ppm/°C drift.
Mold Compound Shrinkage
Volumetric Strain
Thermosetting epoxy resins used in plastic integrated circuit packaging undergo volume reduction during polymerization and cooling processes. Chemical cross-linking during heat curing contracts polymer matrices, while subsequent cooling causes further thermal contraction. Differences in thermal expansion coefficients between silicon dies, die pads, and epoxy compounds create permanent residual mechanical stress.
Mold compound shrinkage exerts compressive force on embedded silicon dies, altering analog circuit performance through piezoresistive effects.
Stress Management
Formulations with high silica filler content reduce overall thermal expansion coefficients and minimize volumetric contraction. Silica particles lower total resin content, decreasing chemical shrinkage during post-mold curing cycles. Flexible stress-absorbing die coating layers cushion silicon surfaces against direct compression from surrounding epoxy matrices.
Symmetrical package construction balances mechanical forces across top and bottom die surfaces to prevent package warping.
Dimensional Inspection
Laser profilometers measure dimensional changes and warpage in packaged integrated circuits after mold curing. Analytical balances verify density changes occurring within mold compound samples during cross-linking reactions. Standard test procedures determine linear and volumetric shrinkage percentages for packaging materials.
Strain Limit
Package stress limits constrain allowable die size and compound formulations for precision analog devices. Excessive compressive strain alters resistor values and shifts transistor threshold voltages beyond calibration adjustment limits. Qualification standards require stable mechanical dimensions following repeated thermal conditioning cycles.