Interconnect Structure
High density printed circuit board architecture places blind laser-drilled vertical interconnects directly within surface mount landing pads. A micro-via in pad enables direct routing from surface component pads to internal signal layers, eliminating fan-out traces and reducing circuit inductance. This structural layout governs routing density and signal integrity in fine-pitch electronic assemblies.
The design configuration minimizes parasitic capacitance by shortening interconnect path lengths. The design stops applying when hole aspect ratios exceed manufacturing limits or when components require un-plated non-conductive pad surfaces.
Solder Escape
Placing un-filled micro-vias directly in solder pads causes solder paste to wick into the hole during reflow soldering. Void formation and insufficient solder volume at the component termination result from un-capped structures. Copper electroplating completely fills the micro-via prior to planarization and outer layer processing.
Capping the filled structure creates a flat copper surface that prevents solder loss during reflow operations.
Verification Process
Cross-sectional metallography and x-ray inspection verify hole filling completeness and surface planarity. Optical profilometers measure dimple depth over capped vias to ensure compliance with flatness standards. IPC specifications set allowable dimple thresholds to prevent void formation beneath ball grid array packages.
Plating Defect
Inadequate copper plating thickness creates target pad separation during thermal stress. Impurities in plating baths cause interface voiding between copper cap and filled via barrel. Thermal cycling stresses cause target pad lifting, leading to intermittent electrical opens in field deployment.
Micro-via in pad structures require precise control of electroplating chemistry to maintain mechanical integrity.
