Internal Bandgap Voltage Error Reduction in High Gradient Layouts
Internal bandgap voltage errors in high gradient layouts are reduced by common-centroid matching, thermal isolation trenching, and package stress mitigation.
Mechanical Strain Tensor
Deformation Analysis
Mathematical matrices describe the three-dimensional deformation of a solid body under applied external forces. Analyzing the mechanical strain tensor allows silicon designers to predict how packaging processes and thermal expansion warp the silicon crystal and alter the performance of integrated sensors.
Piezoresistive Coupling
The components of the strain tensor map directly to changes in the resistivity of the silicon substrate. Shear and normal strains affect the mobility of charge carriers in different ways depending on the crystal orientation. This coupling can introduce unwanted offsets in precision bandgap references and operational amplifiers.
Package Stress
When an integrated circuit is soldered onto a printed circuit board, the differing expansion rates of the board, solder and mold compound create complex internal forces. The resulting strain tensor varies across the surface of the die, peaking near the corners and edges. Engineers use finite element modeling to simulate these stress patterns and locate sensitive analog blocks in the low-stress center of the chip.
This simulation guides the placement of stress-isolation trenches.
Metrological Validation
Verifying these simulations involves measuring the offset voltages of stress-sensitive test structures across a wide temperature range. High-precision calibration systems apply controlled bending forces to the completed board to isolate the stress coefficients. The results are used to refine the mechanical models.