Measurement Standard
Microelectronic package evaluation under thermal stress is standardized by an industry-approved procedure for measuring board-level warpage. The jesd22-b112 standard defines the methods for capturing surface coplanarity changes of semiconductor devices during thermal reflow cycles. This protocol ensures that packaging and assembly facilities employ uniform techniques to evaluate device flatness.
Metrological Procedure
Compliance with this standard requires the use of shadow moire, digital image correlation, or projection moire systems to measure the dynamic out-of-plane displacement of the component. The jesd22-b112 document specifies the required grid resolution and temperature profile accuracy needed to achieve repeatable data. Calibration of the optical sensor and heating chamber is validated against standard quartz reference targets.
This rigorous process reduces measuring uncertainty across different laboratory sites.
Reference Baseline
Measuring flatness across a temperature sweep yields a profile of the package behavior under actual soldering conditions. The standard establishes the baseline flatness at room temperature and compares it to the peak reflow state.
Substrate Deviation
Automated analysis software uses the gathered displacement field to calculate the maximum warp at each specified temperature step. Manufacturers utilize the results of the jesd22-b112 evaluation to qualify new packaging materials and substrate thicknesses before volume production. High warpage values during the heating cycle indicate a risk of solder bridging or open joints during board assembly.
By standardizing this measurement, the microelectronics industry ensures consistent reliability metrics across the supply chain.
