Internal Bandgap Voltage Error Reduction in High Gradient Layouts
Internal bandgap voltage errors in high gradient layouts are reduced by common-centroid matching, thermal isolation trenching, and package stress mitigation.
Wafer Level Trim
Prototyping Adjustments
Calibration of integrated circuits on the undivided semiconductor wafer adjusts analog parameters before the devices are diced and packaged. Applying a wafer level trim enables the correction of systematic manufacturing variations across the wafer, which maximizes the yield of high-precision components.
Trimming Technologies
Probe cards contact the micro-pads of each die while a laser or electrical pulse modifies internal resistors. Thin-film resistors are trimmed by vaporizing a portion of the resistive material to increase the resistance. Alternatively, electronic fuses are blown to permanently set the calibration bits in the design.
Post Assembly Verification
While this step corrects for wafer-level process variations, it cannot account for the mechanical stresses introduced during dicing and packaging. Packaging processes can shift the calibrated parameters, requiring a secondary trim or calibration step after assembly. Therefore, designers must budget for these packaging shifts when specifying the wafer-level trim limits.
The combination of both wafer and package-level tuning provides the highest accuracy for critical applications. This dual-trim strategy ensures that the final packaged devices meet the tightest performance specifications.
Calibration Cycle
Automated test sequences execute the trimming process by measuring the circuit output, calculating the trim target and applying the laser or pulse. This cycle is completed in milliseconds for each of the thousands of die on a wafer. The results are recorded in the factory database for quality tracking.