Integrated Protection
Semiconductor packaging processes apply protective covers and hermetic seals over entire silicon wafers prior to individual die dicing. Integrated capping technologies seal micro-electromechanical sensing elements inside controlled cavities at the wafer stage. Executing wafer-level encapsulation protects delicate sensor structures from contamination and mechanical damage during downstream manufacturing handling.
High-volume processing steps lower unit cost while maintaining precise cavity volume tolerances.
Hermetic Sealing
Anodized bonding or metallic transient liquid phase bonding joins cap wafers to active device wafers. Maintained cavity pressure controls damping properties in resonant micro-structures and resonant pressure sensors. Outgassing from bonding adhesives or metal layers alters internal cavity pressure and changes resonant frequency baselines over operational lifetimes.
Gettering materials deposited inside sealed cavities absorb residual gases to maintain vacuum stability over extended timeframes. Optical interferometry measures cap deflection to verify hermetic seal integrity without destructive physical testing. Shear strength testing assesses bond line mechanical strength under environmental thermal shocks.
Stress Distribution
Cap wafer attachment introduces mechanical stress into the sensor substrate due to thermal expansion coefficient mismatches. Residual bonding stress shifts sensor zero-offset values and alters thermal sensitivity profiles. Characterizing wafer-level encapsulation stress helps optimize protective cap thickness and bonding temperature profiles.
Leakage Boundaries
Helium leak detection standards define maximum permissible gas leakage rates into internal cap cavities. Acceptance testing guarantees vacuum stability across required operational temperature bounds.
