Selecting Surface Mount Packaging Formats for Digital Environmental Sensors
Selecting surface mount sensor packages requires balancing land-pattern mechanical stress and reflow limits against bus integration effort and unit yield cost.
Wafer Level Chip Scale Packaging
Packaging Technology
Packaging of integrated circuits at the wafer level removes the need for individual wire bonding by creating interconnections before the silicon is diced. In wafer level chip scale packaging, the resulting package is nearly the same size as the silicon die itself. This approach eliminates the need for traditional wire bonding or plastic molding steps used in conventional assembly.
The final product is a compact component that is ready for surface mount assembly.
Interconnection Layer
Thin films of dielectric and metal are deposited directly onto the surface of the wafer to redistribute the electrical contacts. Within wafer level chip scale packaging, these redistribution layers route the signals from the dense central pads of the chip to a wider array of solder bumps. Bumps provide the mechanical and electrical connection to the printed circuit board.
Advanced lithography allows for extremely high density routing that is not possible with traditional packaging.
Manufacturing Advantage
Processing thousands of chips simultaneously on a single wafer reduces the cost per unit and improves the consistency of the electrical characteristics. Wafer level chip scale packaging also offers superior thermal performance because the heat path from the silicon to the board is very short. Testing and burn in can be performed at the wafer level, which simplifies the supply chain and reduces the handling of individual parts.
Modern fabrication facilities use high precision thinning and dicing techniques to ensure the integrity of the die edges after the packaging steps are complete. The resulting components provide the smallest possible footprint for a given function, allowing for the design of extremely thin and compact consumer electronics.
Mechanical Reliability
The absence of a protective plastic housing makes the silicon die more susceptible to physical damage during the assembly process. In wafer level chip scale packaging, the mismatch in thermal expansion between the silicon and the board substrate can put measurable stress on the solder joints. Underfill materials or specific solder ball alloys are often used to improve the fatigue life of these connections.