Silicon Substrate Thermal Expansion Mechanics in Micro Inertial Sensors
Silicon substrate thermal expansion alters MEMS structural spacing and compliance, requiring isolated single-point anchors and 3rd-order ASIC polynomial correction.
SOI MEMS
Silicon Substrate
Microelectromechanical systems utilize layered silicon-on-insulator wafers to create precise mechanical and electrical structures on a single substrate. The technology known as soi mems uses the embedded silicon dioxide layer as an etch stop to define the thickness of the moving silicon parts. This construction provides superior mechanical stability and electrical isolation compared to traditional bulk silicon structures.
Microstructure Fabrication
Device fabrication on these wafers allows for the creation of high-aspect-ratio structures with very low internal stress. In soi mems, the top silicon layer is patterned and etched to form the movable membranes or cantilever arms of sensors. The insulating oxide layer underneath is then selectively etched away to release these structures so they can move freely.
This approach is widely used to manufacture high-performance accelerometers and gyroscopes. This simplifies the manufacturing flow.
Metrological Inspection
Inspection of these microstructures uses scanning electron microscopy and optical profilometry to measure the dimensions and flatness of the released parts. These measurements verify that the etching process has completely cleared the oxide layer without damaging the silicon springs. This step is critical for ensuring that the mechanical stiffness matches the design specification.
The analysis is performed on test structures on each wafer.
Operational Limit
High operating voltages can cause electrostatic pull-in of the microstructures if they are designed too close to the substrate. This physical limitation means that the operating voltage must be kept below a critical threshold to prevent permanent latch-up or damage to the device.