Internal Bandgap Voltage Error Reduction in High Gradient Layouts
Internal bandgap voltage errors in high gradient layouts are reduced by common-centroid matching, thermal isolation trenching, and package stress mitigation.
Reflow Hysteresis
Thermal Shift
Unrecoverable shifts in the electrical parameters of an integrated circuit occur after it is subjected to the high temperatures of a solder reflow cycle. This reflow hysteresis manifests as a permanent change in the sensor offset and gain, caused by the cooling and solidification of the mold compound and solder joint.
Material Interaction
During reflow, temperatures reach over two hundred and sixty degrees Celsius, which exceeds the glass transition temperature of the packaging materials. As the board cools, the materials shrink at different rates, locking in new mechanical stresses. These changes alter the electrical behavior of the silicon through piezoresistive effects.
Design Mitigation
Mitigating this hysteresis requires using advanced packaging materials with low shrinkage and matched thermal expansion coefficients. Silicon-level techniques include placing sensitive circuitry in stress-isolated regions of the die or utilizing on-chip stress sensors to dynamically compensate for the offset shifts. Software-level corrections can also be applied if the sensor is recalibrated after board assembly.
This recalibration is often the only way to achieve sub-millivolt accuracy.
Offset Measurement
Characterization of this effect is performed by measuring the sensor outputs before and after a standard reflow profile. The difference between these measurements defines the hysteresis specification of the device. This value is recorded in the datasheet to help system designers estimate the total error budget.