Parasitic Light Sensitivity Limits in Stacked Backside Illuminated Global Shutter Image Sensors
Stacked BSI global shutter sensor parasitic light sensitivity depends on silicon depth, metal shield alignment, and active illumination wavelength.
Pinned Memory Diode
Storage Architecture
Solid-state global shutter architectures integrate specialized photo-diode structures capable of storing charge with low noise and zero image lag. A pinned memory diode combines a buried storage junction with an upper pinning layer to fix surface potential, eliminating interface state thermal generation. Charge transfers completely from the primary photodiode into this pinned structure, preserving signal voltage until readout occurs through the floating diffusion node.
Noise Mechanism
Surface pinning isolates stored electrons from oxide interface defects that generate dark current noise. Integrating a pinned memory diode within global shutter pixels reduces dark signal non-uniformity and residual image lag during fast frame exposures. Complete charge transfer relies on precise potential gradient steps engineered through multi-step ion implantation.
Imbalance in potential profile creates potential barriers or pockets that trap electrons, causing incomplete transfer and image ghosting across sequential frames.
Performance Verification
Testing protocols measure noise performance and charge transfer efficiency under shutter operation. Characterization systems record dark current rates at elevated temperatures to confirm effective surface pinning. Optical test setups measure residual signal remaining in storage nodes after transfer cycles, verifying complete charge transfer across operational clock speeds.
Datasheet compliance requires zero detectable lag under standard operating conditions.
Scaling Boundary
Complex implant structures limit minimum achievable pixel pitch.