Elastoresistive Scaling
Mechanical stress fields applied to crystalline semiconductors induce fractional changes in electrical resistivity proportional to local strain tensor components. The piezoresistive sensitivity quantifies the magnitude of this fractional resistivity variation per unit of applied mechanical stress or strain along designated crystallographic axes. Expressed via gauge factors or piezoresistive coefficients, this conversion metric dictates the output voltage yield of integrated Wheatstone bridge circuits per unit of mechanical input.
The metric ceases to apply once strains exceed material yield thresholds, when silicon transitions into plastic deformation, or under extreme strain levels where elastoresistive relationships deviate from linear proportionality.
Crystallographic Dependence
Piezoresistive response magnitudes depend strictly on dopant species, impurity carrier concentrations, ambient operating temperatures, and crystalline orientations. In p-type single-crystal silicon, the piezoresistive effect peaks along the direction, governed by valence band splitting that redistributes holes into sub-bands characterized by differing effective masses. In n-type silicon, optimal conduction coefficients align along the crystallographic axis, driven by electron transfers between anisotropic conduction band valleys.
Heavy impurity doping reduces the temperature coefficient of resistance while depressing absolute sensitivity, forcing an engineering compromise between high signal output and thermal stability. Temperature escalation reduces the piezoresistive coefficient as thermal energy smears carrier distributions across the splitting energy states.
Thermal Drift
Uncompensated temperature shifts introduce substantial span errors and zero-offset drift within downstream measurement circuits. Differential resistance changes across balanced bridge arms track temperature through intrinsic temperature coefficients of resistance, producing an unbalance voltage independent of applied physical strain. Temperature-induced shifts in sensitivity require passive thermistor matching, localized temperature sensing elements, or digital polynomial correction algorithms within integrated signal conditioning application-specific circuits.
Transducer packaging materials with thermal expansion coefficients mismatched to silicon introduce parasitic thermal stresses, masquerading as mechanical measurands.
Calibration Verification
Measurement protocols establish piezoresistive scaling by applying calibrated mechanical bending moments across micromachined test coupons or cantilever calibration bars. High-precision four-point bending rigs deliver uniform surface stress fields, while automated bridge instrumentation captures voltage shifts across precision constant-current or constant-voltage excitations. Calibration cycles verify forward and reverse strain steps to establish hysteresis percentages, linearity errors, and repeatability tolerances against secondary reference standards.
Gauge factors are confirmed by correlating measured resistance fractional shifts against optical strain-field registrations acquired through digital image correlation. Testing protocols verify that zero-measurand bridge offsets remain stable across extended thermal dwell regimes to ensure metrological traceability.
