Silicon Piezoresistive Bridge Thermal Offset Physics Basics
Silicon piezoresistive thermal offset stems from resistor TCR imbalances and package thermal stress, requiring targeted drive excitation and polynomial compensation.
Passive Thin Film Trimming
Resistor Calibration
Electrical modification of resistive elements on a substrate before the integration of active semiconductor components determines the static performance of a precision analog circuit. Manufacturing lines employ passive thin film trimming to adjust the baseline resistance of individual resistors on a ceramic or silicon wafer. This process is executed prior to packaging the device, allowing the manufacturer to establish precise starting resistor ratios.
It represents the first phase of calibration for high-performance signal conditioning electronics.
Laser Execution
Positioning systems direct a laser beam to vaporize specific portions of the thin metal-alloy film, thereby increasing the resistance of the targeted element. The trim is performed on an unpowered wafer by measuring the resistance between probe pins placed on the device pads. Automated equipment compares each value against a mathematical model to calculate the exact amount of material that must be removed.
This offline step establishes a solid foundation for the subsequent active calibration phase.
Thermal Stability
Altering the film structure generates localized thermal stress at the edges of the cut. These stresses can decay over time, causing minor shifts in resistance that can be minimized by utilizing high-stability resistor alloys like nickel-chromium.
Quality Inspection
Microscopic analysis verifies the completeness of each cut and the absence of thermal damage to the surrounding film. Any remaining conductive bridges would degrade the precision of the trimmed resistor network over time. This evaluation ensures that the passive resistor network maintains its calibrated ratio throughout the lifetime of the sensor.