Depletion Current
Semiconductor fabrication creates unintentional reverse-bias current across the barrier known as p-n junction leakage. Thermal generation within the space charge region produces minority carriers that sweep across the interface under an applied electric field. Crystal defects and metallic contamination introduce trap states inside the forbidden bandgap, which accelerates carrier generation far beyond intrinsic semiconductor limits.
Circuit designers must quantify this parasitic metric to preserve charge storage fidelity in dynamic random access memory capacitors and prevent false logic transitions in high-impedance nodes.
Measurement Protocol
Automated test equipment forces a specified reverse voltage across the terminals while an electrometer measures the resulting sub-picoampere current inside a dark shielded fixture. Ambient light generates stray electron-hole pairs that artificially inflate the reading, so operators perform dark box calibrations before every test sequence. Thermal drift severely impacts measurement repeatability, requiring the device under test to settle at a stable temperature plateau before the meter records the data point.
Standard verification routines compare the observed value against data sheet maximum limits at specific reference temperatures set by device qualification standards.
Degradation Mechanism
Manufacturing stresses propagate crystal dislocations into the active depletion layer, where localized electric field crowding multiplies the generation rate through Poole-Frenkel emission. Elevated operating temperatures exponentially increase intrinsic carrier concentration, causing the reverse current to double roughly every ten degrees Celsius. Ionic contamination from chemical residues migrates along passivation boundaries, creating microscopic conductive shunts that bypass the bulk semiconductor material entirely.
Radiation exposure displaces lattice atoms, permanently increasing defect density and elevating the reverse-bias current throughout the operational lifetime of the component.
Thermal Drift
Elevated junction temperatures drive minority carrier generation rates upward, producing an exponential expansion in leakage magnitude that compromises low-power circuit operation. Circuit engineers calculate thermal dissipation limits by measuring the leakage current at known elevated temperatures against baseline ambient references. Standard calibration procedures account for this temperature dependency by applying correction algorithms to the recorded electrical parameters before final sorting.
Thermal runaway occurs when excessive leakage current increases power dissipation, which raises the local temperature and further accelerates the parasitic current generation process.
