Interface Standard
Hardware protocols for testing printed circuit boards and integrated circuits define a four wire or five wire serial interface for accessing internal diagnostic registers. Adherence to ieee 1149.1 allows engineers to verify the electrical connections between chips without using physical probes. This standard is the foundation for boundary scan technology.
Protocol Sequence
Operations start with a specific state machine sequence on the test mode select line that puts the device into a mode where it can receive instructions. Once in this state, ieee 1149.1 allows the test controller to shift data into the instruction register to select which internal scan chain to access. Data then flows through the serial lines to either read the state of the pins or to force them to a specific logic level.
Diagnostic Coverage
Designers use this interface to find manufacturing defects such as short circuits, open traces, solder bridges or missing components on a densely populated board. Because ieee 1149.1 provides direct access to the pins of the chip, it can identify a failure even when the chip itself is not fully functional. This capability reduces the time required for failure analysis in the factory and in the field.
Design Integration
Silicon vendors must include the specific boundary scan cells and the test access port in their chip designs to be compliant. These components occupy a small amount of area but provide a massive improvement in testability.
