Communication Delay
Temporal delay between the initiation of a data transfer request and the actual arrival of the payload at the receiving node determines the maximum sample rate of a digital sensor. An i2c bus latency arises from the combined effects of clock stretching and bus arbitration. This delay limits the responsiveness of real time control loops.
Protocol Timing
Rise times and falling edges contribute to the total time required for a bit to settle on the wire. High parasitic capacitance on the signal lines increases i2c bus latency by slowing the charging of the pull up resistors. Designers reduce these delays by selecting lower resistance values or minimizing trace length.
Throughput Impact
Increased i2c bus latency reduces the effective bandwidth. Software drivers must wait for the acknowledgment bit before proceeding with subsequent operations. Traffic congestion on the bus further compounds the wait times for low priority devices.
Clock Stretching
Slaves may hold the clock line low to stall the master while processing internal tasks. Excessive i2c bus latency from clock stretching indicates an imbalance between the bus speed and the processing capability of the peripheral. System performance degrades when these delays exceed the timeout period of the master controller.
