Interconnection Structure
Semiconductor die mounting is achieved by inverted placement of the silicon substrate onto a carrier board using conductive solder bumps. This design allows the flip chip configuration to establish electrical connections directly across the active surface of the die.
Metrological Inspection
Quality control of inverted silicon packages depends on x-ray imaging to verify solder joint integrity and find internal voids. When validating flip chip bonds, measurements must detect micron-level coplanarity variations across the array of solder balls. Alignment systems must register the die to the substrate with sub-micron precision to prevent electrical open circuits.
Automated optical systems inspect the bump heights before reflow to ensure uniform contact during assembly.
Thermal Strain
Differences in the thermal expansion coefficient between the silicon die and the organic substrate generate shear stress on the solder bumps during thermal cycling. This mismatch represents a major risk to the long-term reliability of the flip chip assembly. Underfill materials are applied beneath the die to distribute this mechanical stress across the entire package area.
Without this supportive material, the solder connections would rapidly fail under cyclic stress.
Deposition Process
The deposition of under-bump metallization layers on the wafer surface is a prerequisite for reliable solder bump attachment. These metal layers prevent intermetallic diffusion and provide a solderable surface for the flip chip bumps. Electroplating or ball placement techniques must be qualified to ensure uniform deposit thickness across the wafer.
If the thickness varies, the reflow process will produce uneven joints and cause assembly failures. Regular calibration of the sputtering and plating equipment ensures the thickness remains within the specified ten percent window.
