Bias Instability Figures That Decide Whether Dead Reckoning Holds
Inertial dead reckoning holds only while gyroscope bias instability bounds cubic tilt divergence within allowable spatial position tolerance thresholds.
Delta Sigma Digitizer Noise Floor
Metrological Floor
The residual electrical variance measured at the converter terminals without an applied input signal defines the delta sigma digitizer noise floor. Measuring this floor requires terminating the analog inputs with a matched impedance while the clock generator runs at the intended sample frequency. Thermal agitation in resistors and semiconductor junctions generates the baseline voltage fluctuations that constitute this parameter.
Quantization error, which originates from the finite resolution of the internal feedback loop, mixes with electronic circuit noise to establish the lower boundary of detectable signals. Engineers verify this characteristic during factory calibration using shielded enclosures that block electromagnetic interference from external sources. Environmental factors such as ambient temperature shifts and power supply ripple degrade the baseline performance during field deployment.
Regulatory bodies do not set a universal tolerance for this specification, leaving manufacturers to declare the performance metric on individual data sheets under specified reference conditions.
Quantization Limit
Oversampling ratios determine how effectively the internal digital filter pushes high frequency quantization errors out of the usable bandwidth. Lower oversampling rates concentrate less noise shaping power, leaving a higher residual amplitude across the passband. Modulator order dictates the slope of the noise shaping curve, where higher order loops achieve steeper attenuation of low frequency disturbances.
Clock jitter introduces phase noise that folds back into the conversion band, raising the measured baseline despite ideal component selection. Power supply rejection ratio limits dictate how much switching regulator frequency components leak into the reference voltage inputs.
Circuitry Variance
Thermal electron movement inside the feedback DAC resistors produces Johnson noise that scales with absolute temperature. Semiconductor substrate coupling introduces substrate noise from digital logic switches into sensitive analog input nodes. PCB layout parasitics create stray capacitance paths that allow high frequency digital return currents to mix with low level analog references.
Verification Protocol
Testing demands specialized signal generators with ultra low phase noise to isolate hardware limits from source contamination. Shielding efficiency determines whether ambient radio frequency interference penetrates the enclosure and elevates the reading. Proper grounding schemes prevent ground loop currents from flowing through the sensitive return paths of the conversion stage.
Post processing software extracts root mean square voltage levels from long time domain captures to yield the final numerical index. Manufacturers publish these verified limits to establish the absolute resolution boundary of the acquisition hardware.