Calculating Group Delay in Delta Sigma Converters
Delta-sigma converter group delay equals the phase derivative across decimation filter stages, calculated as K times M minus one divided by twice the modulator clock for sinc filters.
Continuous-Time Delta-Sigma
Metrological Definition
Continuous-Time Delta-Sigma acts as a continuous-time analogue-to-digital conversion architecture that processes input signals through active filtering before sampling occurs inside a clocked quantiser. This topology replaces the traditional switched-capacitor network of discrete-time counterparts with continuous-time loop filters built from resistors, capacitors and operational transconductance amplifiers. Continuous-time loop filters inherently provide built-in anti-aliasing attenuation directly at the conversion node, eliminating external passive filter stages that otherwise introduce insertion loss and thermal noise.
Quantisation error is pushed toward high frequencies through noise shaping, while the feedback DAC subtracts reconstructed signals at the summing junction. Calibration protocols verify loop coefficient accuracy against reference voltage standards to maintain stability across temperature shifts. Circuit nonlinearities in the feedback DAC degrade dynamic range because pulse-width jitter on the reference clock converts directly into voltage errors at the sampling instant.
Production testing evaluates integrated nonlinearity and signal-to-noise ratio under specified input frequencies, establishing factory calibration limits before deployment in communication channels.
Clock Jitter
Timing uncertainty in the sampling clock degrades conversion fidelity by altering the charge transferred during each feedback DAC pulse. Analytical models correlate phase noise variance with signal distortion, demonstrating that larger input slew rates magnify the voltage error produced by identical time offsets. Differential circuitry suppresses common-mode noise sources, yet residual mismatch between differential paths still generates harmonic distortion products that calibration routines must measure and compensate.
Circuit designers select low-phase-noise crystal oscillators to minimise high-frequency degradation, establishing baseline performance metrics that field verification procedures subsequently check against factory certificates.
Filter Synthesis
Continuous-time loop filter coefficients derive from discrete-time equivalent prototypes through impulse invariance transformations that account for excess loop delay introduced by comparator propagation times and logic overhead. Stability boundaries narrow as feedback delay increases, requiring compensation networks within the operational amplifier stages to preserve phase margin. Component aging alters resistor and capacitor values, producing pole-zero migration that shifts the noise shaping notch away from direct current and degrades overall resolution.
Automated test equipment measures frequency response deviations across the operational band, verifying that temperature compensation circuits successfully counteract component drift without exceeding designated tolerance limits set by the manufacturer.
Quantiser Resolution
Multi-bit internal quantisers reduce feedback DAC jitter sensitivity by decreasing the step height of each feedback transition while relaxing slew rate requirements on the preceding integrator stages. Thermal noise generated by input resistors establishes the fundamental noise floor, limiting the minimum resolvable signal amplitude regardless of loop order or clock frequency enhancements. Production test suites isolate quantiser metastability errors by sweeping input amplitudes near decision thresholds, confirming that error correction logic prevents bit misinterpretation during high-speed transitions.
Final verification certificates record achievable dynamic range under reference operating conditions, bounding the operational envelope where specified conversion performance remains guaranteed.
Dynamic Thermal Gradient Modeling for High Precision MEMS Gyroscope Zero Rate Shift Compensation
Dynamic thermal gradient compensation requires multi-node spatial sensing and state-space filtering to eliminate phase-lagged bias shifts during rapid thermal slewing.