Silicon Die Revision Register Verification Basics
Verifying silicon die revision registers during boot ensures firmware compatibility and prevents unannounced stepping changes from causing field failures.
Boundary Scan JTAG
Hardware Architecture
Embedded logic structures allow the inspection and control of internal pins on an integrated circuit without requiring physical probe access. Using boundary scan jtag permits the verification of interconnects between surface-mount devices where traditional test points are absent. The standard defines a serial interface for shifting test data through a chain of components.
Operation Logic
Operation relies on a state machine known as the test access port controller which moves through sixteen distinct states based on the clock and mode select signals. Each chip contains a boundary scan register where individual cells sit between the core logic and the package pins. This arrangement allows the tester to drive a signal on one chip and capture it on another to confirm electrical continuity across the PCB interconnects.
Fault Diagnosis
Diagnosis of shorts or opens occurs by comparing the captured serial bit stream against a known good pattern. While the method provides coverage for digital nets, it struggles with purely analog circuits unless specialized extensions are implemented. The speed of the scan clock often limits the total time needed to cycle through complex board designs containing thousands of nodes.
Signal Constraint
Signal integrity during the test depends on the stability of the clock signal and the avoidance of ground bounce during simultaneous switching of boundary cells. Overshoot on the data lines can cause false readings or latch-up in sensitive devices. External pull-up resistors on the reset line ensure the circuit remains in a safe state during normal functional operation.