Precision Bandgap Thermal Stress Error Reduction across Surface Mount Packages
Mitigate bandgap thermal stress errors using compliant leaded packages, PCB isolation slots, polyimide die buffers, and stabilized factory calibration.
Quad Common Centroid
Geometric Layout
A two-dimensional spatial arrangement places four matched electrical components in a cross-coupled configuration around a central point. This quad common centroid geometry distributes physical parameter variations symmetrically.
Gradient Cancellation
Thermal and process gradients on a semiconductor die can cause severe mismatches between adjacent resistors or transistors. By splitting two matched devices into four distinct sub-components and placing them diagonally opposite each other, the quad common centroid layout cancels out the linear variations. The averaging of the parameters across the shared center of symmetry minimizes the net mismatch to almost zero.
Stress Elimination
Mechanical stress gradients originating from package mounting and molding compound shrinkage also introduce non-uniformities across the silicon surface. This geometric layout distributes the stress-induced changes equally among the cross-coupled elements, which prevents differential offsets in sensitive analog circuits. Stable performance under varying mechanical loads is achieved because the common-mode stress is rejected by the differential sensing architecture.
Design Complexity
Routing the interconnects for a four-component symmetrical layout requires a sophisticated multi-metal wiring scheme to ensure that parasitic resistances and capacitances are perfectly balanced. Although this routing increases the silicon area and design time, the resulting matching accuracy cannot be achieved through simple side-by-side placement. The performance boost justifies the added complexity in high-performance analog-to-digital converters and precision bandgap voltage references.