Structural Component
Performance benchmarks for new fabrication processes require the evaluation of isolated circuit components away from the main wafer array. An iso die provides a controlled environment for characterizing leakage currents and breakdown voltages at the transistor level. This configuration is used during the qualification of new fabrication processes.
It allows the characterization of electrical properties without the interference of neighboring circuits.
Isolation Methodology
Physical separation involves dicing the wafer into distinct squares or rectangles using a diamond saw or a laser. The quality of an iso die depends on the cleanliness of the cut and the absence of micro-cracks at the edges. Contaminants from the cooling water or the dicing tape can migrate to the bond pads.
Metrologists inspect the perimeter to ensure that the active area is not compromised by the mechanical stress of the dicing process.
Measurement Standard
Reference conditions for electrical probing are established to ensure repeatable results across different laboratory setups. Testing an iso die requires a probe card that matches the contact layout exactly. The contact resistance between the probe tip and the aluminum pad is a common source of measurement error.
Regular cleaning of the probe tips and calibration of the test equipment are necessary to maintain a precision of one millivolt or less. Documentation of the probe force and the scrub length ensures that the pad surface is not excessively damaged during the test cycle.
Reliability Factor
Thermal resistance of the standalone part differs from that of a device in a multi-chip module. Heat dissipation in an iso die is primarily governed by the die attach material and the leadframe.