Precision Bandgap Thermal Stress Error Reduction across Surface Mount Packages
Mitigate bandgap thermal stress errors using compliant leaded packages, PCB isolation slots, polyimide die buffers, and stabilized factory calibration.
Factory Trimming
Calibration Process
An automated post-fabrication adjustment alters the internal electrical parameters of an integrated circuit during the manufacturing stage. This factory trimming procedure corrects for wafer-level processing variations.
Technological Execution
Laser cutting or electrical fusing modifies the value of thin-film resistor networks on the silicon surface. High-precision instruments measure the device output in real time while a computer control system directs the beam or current pulses to adjust individual resistors. This interactive loop continues until the target parameter falls within specified limits.
Voltage Reference
A voltage reference source requires precise resistor ratio matching to achieve a zero-temperature-coefficient output. Through factory trimming, the temperature-dependent drift can be minimized to a fraction of a millivolt per degree. Testing systems execute this calibration at several temperature points to ensure the compensation circuit performs across the entire operating range.
Operational Limit
Thermal stress encountered during subsequent packaging assembly can undo some of the improvements achieved through these early calibration steps. If the silicon die shifts slightly inside the molded package, the induced stress changes the resistance values and causes the output to drift from the trimmed value. This limitation requires designers to account for post-assembly stress or include on-chip memory for end-of-line recalibration.