Architecture Description
Decimation and interpolation stages often utilize a multiplierless hardware structure to change the sampling rate of digital data streams. The cic filter consists of a series of integrator stages followed by a sequence of comb stages. It provides a computationally efficient way to process high speed signals from delta sigma converters.
Computational Efficiency
Avoiding the use of hardware multipliers reduces the power consumption and silicon area required for the processing block. Because the system relies solely on addition and delay elements, it handles wide bit widths at extremely high clock frequencies. The bit growth through the integrator chain requires careful bit width allocation to prevent mathematical overflow.
Passband Performance
The frequency response of this structure follows a sinc function, which provides substantial attenuation at multiples of the decimation frequency. Higher order designs increase the stopband rejection but also introduce a steeper roll off in the desired signal band. A secondary compensation filter usually follows the main block to flatten the frequency response before final data delivery.
Integration Limit
Hardware implementation requires a fixed word length that accommodates the maximum possible gain of the filter stages. Fixed point arithmetic ensures that the internal wrap around in the integrators does not corrupt the final signal as long as the output word is wide enough.
