Physical Separation
Dielectric distance between fixed electrodes and moving proof masses defines the primary electrostatic interface in micro-machined capacitive sensors. Within the structural layout of a capacitive MEMS device, the capacitive transduction gap specifies the spatial dimension across which electrostatic forces and capacitance changes are generated. This physical parameter dictates the magnitude of parallel-plate capacitance, governing motion sensitivity and electrostatic actuation force per volt.
It sets the boundary where linear displacement approximations remain valid, beyond which pull-in instability dominates mechanical behavior. The metric ceases to govern device response when physical electrode contact occurs or when dielectric breakdown limits operational voltage.
Electrostatic Coupling
Electrostatic force generation scales inversely with the square of electrode separation, creating non-linear electromechanical feedback. As the capacitive transduction gap narrows under acceleration or tuning voltages, drive sensitivity increases alongside negative electrostatic spring stiffness. Transducer modeling relies on precision capacitance measurements to extract accurate gap dimensions under zero-bias reference conditions.
Discrepancies between designed and fabricated gap distances directly alter nominal zero-g capacitance and sensitivity scale factors.
Fabrication Sensitivity
Photolithographic limits and high-aspect-ratio silicon etching variations introduce spatial variations in trench width across production wafers. A ten percent reduction in the capacitive transduction gap increases baseline capacitance by eleven percent while shifting the electrostatic pull-in voltage downward by fifteen percent. Sensor qualification protocols require automated wafer-prober testing to map cross-wafer gap uniformity prior to packaging.
Out-of-spec gap dimensions trigger automatic trimming of internal charge pump voltages to restore standardized full-scale sensitivity.
Performance Limit
Sensing accuracy depends on maintaining stable gap geometry across environmental extremes. Thermal expansion of silicon and package-induced stress alter the capacitive transduction gap during operation, generating offset drift in acceleration readings. Calibration procedures correct for thermal gap changes using embedded temperature sensor data and multi-point compensation matrices stored in integrated ASIC memory.
Extreme shock events present a mechanical boundary where stop structures prevent electrode collision, protecting the gap geometry from permanent deformation. Verification testing confirms that post-shock zero-g bias remains within specified tolerance limits.
