Silicon Die Revision Register Identification Verification Procedures
Verify silicon die revision registers via JTAG or serial readback before firmware boot to catch unannounced stepping changes and protect assembly yield.
Base Mask ECO
Revision Protocol
Engineering changes at the silicon level require a formal document to authorize modifications to the primary transistor layers of an integrated circuit. When a base mask eco is issued, the layout of the diffusion or polysilicon layers undergoes a redesign to correct a functional error or to optimize the basic transistor performance. These changes occur before the metal interconnects are even considered.
Physical Modification
Layout engineers must carefully adjust the geometry of the active regions to meet the new performance targets specified in the change order. Because a base mask eco involves the lowest layers of the semiconductor stack, it usually necessitates a full production restart. This process is expensive and time consuming.
Timing Impact
Schedules for product release move extensively when the foundation of the chip is altered late in the design cycle. A base mask eco forces the fabrication facility to generate a completely new set of masks for the initial steps of the lithography process. This delay can exceed ten weeks in a typical high volume manufacturing environment.
Manufacturing Workflow
Verification of the new design occurs through rigorous simulation before the first physical wafer is processed. The update is tracked in the product lifecycle management system to ensure that all subsequent batches use the corrected masks.