Electronic Impedance
Unwanted resistive and inductive components along with capacitive effects exist at the connection points between a wafer level chip scale package and the substrate. These wlcsp interface parasitics are lower than those found in traditional leaded packages due to the absence of bond wires and long lead frames.
Signal Quality
The small solder bumps used for the connection provide a short path for signals which reduces the inductance and improves high frequency performance. Despite the small size these wlcsp interface parasitics must be modeled during the design of high speed memory interfaces to ensure proper timing.
Calibration Step
Vector network analyzers characterize the impedance of the interconnects by measuring the reflection and transmission coefficients across a broad frequency spectrum. Accurately accounting for wlcsp interface parasitics allows for the optimization of impedance matching networks on the printed circuit board.
Assembly Risk
Variations in the solder ball height or the alignment of the die during the reflow process can introduce unexpected shifts in the electrical properties of the junction. Stability of wlcsp interface parasitics is a factor in the long term reliability of mobile and wearable electronic devices. The quality of the underfill material also influences the parasitic capacitance between the die surface and the board.
Precision placement of the die minimizes the variation in capacitive coupling between the circuit and its surroundings.
