Polymer Crosslinking Densities Influence Die Attach Creep Rates
Higher crosslink density suppresses polymer die attach creep rates by restricting free volume and extending rubbery plateau modulus under continuous thermal load.
Warpage Displacement
Geometric Distortion
An out-of-plane deformation of a multi-layered substrate or semiconductor package occurs due to the mismatch in the coefficients of thermal expansion of the constituent materials. This warpage displacement can cause serious assembly defects during solder reflow, such as open connections or bridged solder joints. Monitoring this deflection ensures that the package remains within the coplanarity limits required for subsequent automated assembly steps.
Deflection Mapping
Optical profilometry and shadow moire techniques measure this distortion by projecting a series of light fringes onto the package surface to map its three-dimensional topography. The package is heated in a specialized oven to simulate the thermal profile of a solder reflow oven while cameras record the fringe patterns. Software algorithms calculate the out-of-plane displacement at each temperature point, generating a complete profile of the package behavior.
This enables engineers to identify the temperatures at which the warpage is most severe, which helps them design board layouts that minimize the stress.
Boundary Condition
Accurate measurements require that the sample be supported without constraint to allow free thermal expansion and contraction during testing. Constraining the substrate or applying uneven clamping forces introduces external mechanical stresses that distort the results and lead to incorrect coplanarity readings. Reference calibration plates are used to verify the flatness and accuracy of the optical sensor system.
Quality Standard
Industry specifications define the maximum allowable coplanarity variation as a function of the pitch of the solder balls. If the deflection exceeds this limit, the component is rejected because it cannot be reliably soldered to the printed circuit board. Production facilities use this metric to qualify substrate materials and optimize the design of high-density electronic assemblies.